Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
30
REG3/REG4 Enable (EN34, EN3, EN4)
REG3 and REG4 have independent I
2
C enable bits
(EN3, EN4) and a shared hardware-enable input
(EN34). As shown in Figure 5, the EN34 hardware-
enable input is logically ORed with the I
2
C enable bits.
Table 6 is the truth table for the V3/V4 enable logic.
Note that to achieve a pure I
2
C enable/disable, connect
EN34 to ground. Similarly, to achieve a pure hardware
enable/disable, leave the I
2
C enable bits at their default
value (EN3 = EN4 = 0 = off); V3 and V4 cannot be inde-
pendently enabled/disabled using only hardware.
Note: A low MR drives RSO low and returns the I
2
C
registers to their default values: EN3 = 0 and EN4 = 0.
Power Modes
The MAX8660/MAX8661 provide numerous enable sig-
nals (Table 5) and support any combination for enabling
and disabling their supplies with these signals. Table 7
shows several power modes defined for PXA3xx
processors along with their corresponding MAX8660/
MAX8661 quiescent operating currents.
Power-Up and Power-Down Timing
Figure 6 shows the power-up sequence for the Marvell
PXA3xx family of processors. In general, the supplies
should power up in the following order:
1) POWER-UP: V8  V5  V1 and V2  V3 and V4
2) REG6 and REG7 typically power external card slots
and can be powered up and down based on appli-
cation requirements.
Note that the Marvell PXA3xx processor controls
EN1/EN2/EN5 with the same SYS_EN signal, yet Marvell’s
timing diagrams show that V5 is supposed to power up
before V1 and V2. Because of the PXA3xx family’s timing
parameters, most systems connect EN1/EN2/EN5
together and drive them with SYS_EN . When powering
up, this connection ensures that V5 powers up before
V1 and V2 (only when V5 is powered from IN).
Marvell PXA3xx Power
Configuration Register (PCFR)
The MAX8660/MAX8661 comply with the Marvell
PXA3xx power I
2
C register specifications. This allows
the PMIC to be used along with the processor with little-
to-no software development. As shown in Table 9, there
are many I
2
C registers, but since the processor auto-
matically updates the PMIC through its power I
2
C inter-
face, only the REG6 and REG7 enable bits need be
programmed to fully utilize the PMIC.
The Marvell PXA3xx processor contains a power man-
agement unit general configuration register (PCFR).
The default values of this register are compliant with the
MAX8660/MAX8661. However, wake-up performance
can be optimized using this register:
• The PCFR register contains timers for the SYS_DEL
and PWR_DEL timing parameters as shown in Figure
6. Each timer defaults to 125ms. When using the
MAX8660/MAX8661, these timers may be shortened to
2ms to speed up the overall system wake-up delay.
• Enabling the “shorten wake-up delay” function
(SWDD bit) bypasses the SYS_DEL and PWR_DEL
timers and uses voltage detectors on the Marvell
PXA3xx processor to optimize the overall system
wake-up delay.
Figure 5. V3/V4 Enable Logic
EN34
SDA
SCL
PV4
PV3
ON
REG4
PG4
LX4
EN3
EN4
BATT
V4
(VCC_SRAM
)
ON
REG3
I
2
C
PG3
LX3
BATT
V3
(VCC_APPS
)
Table 6. Truth Table for V3/V4 Enable Logic
HARDWARE INPUT I
2
C BITS
EN34 EN3 EN4
V3 V4
0 0 (default) 0 (default) OFF OFF
0 0 1 OFF ON
0 1 0 ON OFF
X11ONON
1XXONON
X = Don’t care.