Datasheet

MAX8660/MAX8660A/MAX8660B/MAX8661
High-Efficiency, Low-I
Q
, PMICs with Dynamic
Voltage Management for Mobile Applications
23
MAX8660
MAX8661
IN
EN1
EN2
IN8
TO IN
V8
V6
IN67 (IN6)
V7
SCL
SDA
SRAD
VCC_IOx
RSO
FROM CPU
SYS_EN
( ) ARE FOR THE MAX8661
RAMP
LBR
(1.25V)
LBO
LBF
(1.20V)
BATT
V1
SET1
PV1
PWM
ON
STEP-DOWN
PWM
REG1
PG1
LX1
TO BATT
V1,
VCC_I0x, VCC_LCD,
VCC_MSL, VDD_USB,
VCC_DF, VDD_CI, VCC_TSI
MAX8660/MAX8660B: 3.3V, 3.0V, 2.85V
MAX8660A: 2.5V, 2.0V, 1.8V
1200mA
(MAX8660/MAX8660A/MAX8660B ONLY)
LATCH
V2
SET2
PV2
PWM
ON
STEP-DOWN
PWM
REG2
PG2
LX2
TO BATT
V2,
VCC_MEM
MAX8660/MAX8660B/MAX8661: 3.3V, 2.5V, 1.8V
MAX8660A: 2.5V, 2.0V, 1.8V
900mA
LATCH
V3
EN34
PV3
PWM
RAMP
ON
STEP-DOWN
PWM
REG3
PG3
LX3
TO BATT
FROM CPU
PWR_EN
V3,
VCC_APPS
0.725V TO 1.8V
(DEFAULT 1.4V for MAX8660/MAX8660A/MAX8661)
(DEFAULT 1.15V for MAX8660B)
1.6A
ADJ
0.725V TO
1.8V
V4
IN5
V5
EN5
PV4
PWM
RAMP
STEP-DOWN
PWM
REG4
PG4
LX4
TO BATT
TO IN, V1 OR V2
V4,
VCC_SRAM
0.725V TO 1.8V
(DEFAULT 1.4V for MAX8660/MAX8660A/MAX8661)
(DEFAULT 1.15V for MAX8660B)
400mA
RAMP
ADJ
1.7V TO
2.0V
ADJ
0.725V TO
1.8V
OPEN-DRAIN LOW BATT OUT
TO nBATT_FAULT
BATTERY
AGND
UVLO
OVLO
AND
BATT
MON
REF
1.25V
TO ALL
BLOCKS
V8,
VCC_BBATT
(3.3V 30mA, ALWAYS ON)
V6,
VCC_CARD1
0V/1.8–3.3V
(DEFAULT 0V) 500mA
V7,
VCC_CARD2
0V/1.8–3.3V
(DEFAULT 0V) 500mA
(MAX8660/MAX8660A ONLY)
RESET
V8 < 2.4V
20ms
SET RATE
RAMP
MR
HARDWARE
RESET INPUT
TO CPU
nRESET
LDO
REG8
LDO
REG7
LDO
REG6
TO V1, V2, OR IN
V5,
VCC_MVT, VCC_BG
1.7V TO 2.0V
(DEFAULT 1.8V)
200mA
LDO
REG5
FROM CPU
SYS_EN
EP
AGND PGND
I
2
C SERIAL
INTERFACE
LOGICAL OR
(FIGURE 5)
Figure 2. Functional Diagram