Datasheet

MAX8655
Highly Integrated, 25A, Wide-Input,
Internal MOSFET, Step-Down Regulator
18 ______________________________________________________________________________________
inductor and output capacitor resulting in a smaller
phase shift and requiring a less elaborate error-amplifier
compensation than voltage-mode control. A simple
series R
C
and C
C
is all that is needed to have a stable,
high-bandwidth loop in applications where ceramic
capacitors are used for output filtering. For other types
of capacitors, due to the higher capacitance and ESR,
the frequency of the zero created by the capacitance
and ESR is lower than the desired closed-loop crossover
frequency. To stabilize a nonceramic output-capacitor
loop, add another compensation capacitor from COMP
to GND to cancel this ESR zero. See Figure 9.
The basic regulator loop is modeled as a power modu-
lator, an output feedback divider, and an error amplifi-
er. The power modulator has DC gain G
MOD(dc)
, set by
g
mc
x R
LOAD
, with a pole and zero pair set by R
LOAD
,
the output capacitor (C
OUT
), and its equivalent series
resistance (ESR). Below are equations that define the
power modulator:
where R
LOAD
= V
OUT
/I
OUT(MAX)
, f
S
is the switching fre-
quency, L is the output inductance, g
mc
= 1/(A
VCS
x
R
L
), where A
VCS
is the gain of the current-sense amplifi-
er (12 typ), R
L
is the DC resistance of the inductor, the
duty cycle D = V
OUT
/V
IN.
K
S
is a slope compensation
factor calculated from the following equation:
When SCOMP is connected to GND, use V
SCOMP
= 1.25V;
when SCOMP is connected to AVL, use V
SCOMP
= 2.5V.
Find the pole and zero frequencies created by the
power modulator as follows:
When C
OUT
comprises “n” identical capacitors in paral-
lel, the resulting C
OUT
= n x C
OUT(EACH)
, and ESR =
ESR
(EACH)
/n. Note that the capacitor zero for a parallel
combination of like capacitors is the same as for an
individual capacitor. Figure 10 is the simplified gain
plot for the f
zMOD
> f
C
case.
The feedback voltage-divider has a gain of G
FB
=
V
FB
/V
OUT
, where V
FB
is equal to 0.7V.
The transconductance error amplifier has a DC gain,
G
EA(DC)
= g
mEA
x R
O
, where g
mEA
is the error-amplifi-
er transconductance, which is equal to 110µS, and R
O
is the output resistance of the error amplifier, which is
30MΩ. A dominant pole (f
pdEA
) is set by the compen-
sation capacitor (C
C
), the amplifier output resistance
(R
O
), and the compensation resistor (R
C
); a zero (f
zEA
)
is set by the compensation resistor (R
C
) and the com-
pensation capacitor (C
C
). There is an optional pole
(f
pEA
) set by C
F
and R
C
to cancel the output capacitor
ESR zero if it occurs near the crossover frequency (f
C
).
Thus:
f
CR
pEA
FC
=
××
1
2π
f
CR
zEA
CC
=
××
1
2π
f
CRR
pdEA
COC
=
×× +
1
2π ()
f
C ESR
zMOD
OUT
=
××
1
2π
f
RC
Lf C
KD
pMOD
LOAD OUT
S OUT
S
=
××
+
×× ×
××−−
[]
⎡
⎣
⎢
⎤
⎦
⎥
1
2
1
2
105
π
π
().
K
VLf
VV R
S
SCOMP S
IN OUT L
=+
××
×− ×
1
120 ( )
Gg
R
R
Lf
KD
MOD dc mc
LOAD
LOAD
S
S
()
.
=×
+
×
××−
()
()
−
[]
⎡
⎣
⎢
⎤
⎦
⎥
1105
MAX8655
C
C
C
F
R
C
COMP
Figure 9. Compensation Components
GAIN
(dB)
FREQUENCY
f
pMOD
f
zMOD
fc
CLOSED LOOP
ERROR
AMPLIFIER
0dB
FB
DIVIDER
POWER
MODULATOR
Figure 10. Simplified Gain Plot for the f
zMOD
> f
C
Case