Datasheet

MAX8650
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. Follow these guide-
lines for good PCB layout:
1) Place IC decoupling capacitors as close to IC pins
as possible. Keep the power ground plane and sig-
nal ground plane separate. Place the input ceramic
decoupling capacitor directly across and as close as
possible to the high-side MOSFET’s drain and the
low-side MOSFET’s source. This is to help contain
the high switching current within this small loop.
2) For output current greater than 10A, a multilayer
PCB is recommended. Pour a signal ground plane
in the second layer underneath the IC to minimize
noise coupling.
3) Connect input, output, and VL capacitors to the
power ground plane; connect all other capacitors to
the signal ground plane.
4) Place the inductor current-sense resistor and capac-
itor as close to the inductor as possible. Make a
Kelvin connection to minimize the effect of PCB trace
resistance. Place the input-bias balance resistor (R5
in Figures 8 and 9) near CS-. Run two closely paral-
lel traces from across the capacitor (C9 in Figures 8
and 9) to CS+ and CS-.
5) Place the MOSFET as close as possible to the IC to
minimize trace inductance of the gate-drive loop. If
parallel MOSFETs are used, keep the trace lengths
to both gates equal.
6) Connect the drain leads of the power MOSFET to a
large copper area to help cool the device. Refer to
the power MOSFET data sheet for recommended
copper area.
7) Place the feedback and compensation components
as close to the IC pins as possible. Connect the
feedback resistor-divider from FB to the output as
close as possible to the farthest output capacitor.
8) Refer to the MAX8650 evaluation kit for an example
layout.
Chip Information
PROCESS: BiCMOS
4.5V to 28V Input Current-Mode Step-Down
Controller with Adjustable Frequency
24 ______________________________________________________________________________________
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
FSYNC
POK
SCOMP
ILIM2
REFIN
SS
COMP
FB
OVP
TOP VIEW
MAX8650
QSOP
MODE
SYNCO
LX
BST
DH
PGND
VL
16
15
9
10
ILIM1
CS-
IN
EN
14
13
11
12
CS+
GND
AVL
DL
+
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 QSOP E24-1
21-0055