Datasheet

Case 2: Crossover frequency is greater than the
output-capacitor ESR zero (f
C
> f
Z_ESR
).
The modulator gain at f
C
is:
G
MOD(FC)
= G
MOD(DC)
x (f
P_LC
)
2
/ (f
Z_ESR
x f
C
)
Since the output-capacitor ESR-zero frequency is high-
er than the LC double-pole frequency but lower than
the closed-loop crossover frequency, where the modu-
lator already has -1 slope, the error-amplifier gain must
have zero slope at f
C
so the loop crosses over at the
desired -1 slope.
The error-amplifier circuit configuration is the same as
case 1 above; however, the closed-loop crossover fre-
quency is now between f
P2
and f
P3
as illustrated in
Figure 8.
The equations that define the error amplifier’s zeros
(f
Z1_EA
, f
Z2_EA
) and poles (f
P2_EA
, f
P3_EA
) are the
same as case 1; however, f
P2_EA
is now lower than the
closed-loop crossover frequency. Therefore, the error-
amplifier gain between f
Z1_EA
and f
Z2_EA
is now calcu-
lated as:
G
EA(f
Z1_EA
- f
Z2_EA
)
= G
EA(FC)
x f
Z2_EA
/ f
P2_EA
= f
Z2_EA
/ (f
P2_EA
x G
MOD(FC)
)
This gain is set by the ratio of R4/R1, where R1 is calcu-
lated as illustrated in the Setting the Output Voltage
section. Thus:
R4 = R1 x f
Z2_EA
/ (f
P2_EA
x G
MOD(FC)
)
where f
Z2_EA
= f
P_LC
and f
P2_EA
= f
Z_ESR
.
Similar to case 1, C2 is calculated as:
C2 = 2 / (π x R4 x f
P_LC
)
Set the error-amplifier third pole, f
P3_EA
, at half the
switching frequency, and let RM = (R1 x R3) / (R1 +
R3). The gain of the error amplifier between f
P2_EA
and
f
P3_EA
is set by the ratio of R4/RM and is equal to
G
EA(FC)
= 1 / G
MOD(FC)
. Then:
RM = R4 x G
MOD(FC)
Similar to case 1, R3, C1, and C3 are calculated as:
R3 = R1 x RM / (R1 - RM)
C1 = 1 / (2π x R3 x f
Z
_ESR)
C3 = C2 / ((2π x C2 x R4 x f
P3_EA
) - 1)
MAX8597/MAX8598/MAX8599
Low-Dropout, Wide-Input-Voltage,
Step-Down Controllers
______________________________________________________________________________________ 21
MAX8597
MAX8598
MAX8599
FB
COMP
C3
C2
R4
R2
R1
C1
R3
L
C
O
REF
Figure 6. Type III Compensation Network
GAIN
(dB)
FREQUENCY
0
f
Z1
f
Z2
f
P2
f
C
f
P3
EA GAIN
CLOSED-LOOP GAIN
Figure 7. Closed-Loop and Error-Amplifier Gain Plot for Case 1
GAIN
(dB)
FREQUENCY
0
f
Z1
f
Z2
f
P2
f
C
f
P3
EA GAIN
CLOSED-LOOP GAIN
Figure 8. Closed-Loop and Error-Amplifier Gain Plot for Case 2