Datasheet

MAX8597/MAX8598/MAX8599
Low-Dropout, Wide-Input-Voltage,
Step-Down Controllers
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I
RMS
has a maximum value when the input voltage
equals twice the output voltage (V
IN
= 2 x V
OUT
), so
I
RMS(MAX)
= I
LOAD
/ 2. Ceramic capacitors are recom-
mended due to their low ESR and ESL at high frequen-
cy, with relatively lower cost. Choose a capacitor that
exhibits less than 10°C temperature rise at the maximum
operating RMS current for optimum long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), the equivalent series inductance
(ESL), and the voltage-rating requirements, which
affect the overall stability, output ripple voltage, and
transient response. The output ripple has three compo-
nents: variations in the charge stored in the output
capacitor, voltage drop across the capacitor’s ESR,
and voltage drop across the capacitor’s ESL, caused
by the current into and out of the capacitor. The follow-
ing equations estimate the worst-case ripple:
where I
P-P
is the peak-to-peak inductor current.
The response to a load transient depends on the select-
ed output capacitor. After a load transient, the output
instantly changes by (ESR x ∆I
LOAD
) + (ESL x di/dt).
Before the controller can respond, the output deviates
further depending on the inductor and output capacitor
values. After a short period of time (see the Typical
Operating Characteristics), the controller responds by
regulating the output voltage back to its nominal state.
The controller response time depends on the closed-
loop bandwidth. With higher bandwidth, the response
time is faster, preventing the output capacitor voltage
from further deviation from its regulation value. Do not
exceed the capacitor’s voltage or ripple current ratings.
MOSFET Selection
The MAX8597/MAX8598/MAX8599 controllers drive
external, logic-level, n-channel MOSFETs as the circuit-
switch elements. The key selection parameters are:
• On-resistance (R
DS(ON)
): the lower, the better.
• Maximum drain-to-source voltage (V
DSS
): should be
at least 20% higher than the input supply rail at the
high-side MOSFET’s drain.
• Gate charges (Q
g
, Q
gd
, Q
gs
): the lower, the better.
Choose MOSFETs with R
DS(ON)
rated at V
GS
= 4.5V. For
a good compromise between efficiency and cost,
choose the high-side MOSFET that has conduction loss
equal to the switching loss at the nominal input voltage
and maximum output current. For the low-side MOSFET,
make sure it does not spuriously turn on due to dv/dt
caused by the high-side MOSFET turning on, resulting in
efficiency degrading shoot-through current. MOSFETs
with a lower Q
gd
/Q
gs
ratio have higher immunity to dv/dt.
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, maximum output current,
and worst-case input voltage (for low-side MOSFET,
worst case is at V
IN(MAX)
; for high-side MOSFET, it could
be either at V
IN(MIN)
or V
IN(MAX)
).
High-side and low-side MOSFETs have different loss
components due to the circuit operation. The low-side
MOSFET operates as a zero-voltage switch; therefore,
the major losses are the channel-conduction loss
(P
LSCC
) and the body-diode conduction loss (P
LSDC
):
P
LSCC
= [1 - (V
OUT
/ V
IN
)] x (I
LOAD
)
2
x R
DS(ON)
P
LSDC
= 2 x I
LOAD
x V
F
x t
dt
x f
S
where V
F
is the body-diode forward-voltage drop, t
dt
is
the dead-time between the high-side MOSFET and the
low-side MOSFET switching transitions, and f
S
is the
switching frequency. The high-side MOSFET operates
as a duty-cycle control switch and has the following
major losses: the channel-conduction loss (P
HSCC
), the
V-I overlapping switching loss (P
HSSW
), and the drive
loss (P
HSDR
). The high-side MOSFET does not have
body-diode conduction loss because the diode never
conducts current:
P
HSCC
= (V
OUT
/ V
IN
) x I
LOAD
2
x R
DS(ON)
Use R
DS(ON)
at T
J(MAX)
:
P
HSSW
= V
IN
x I
LOAD
x f
S
x [(Q
gs
+ Q
gd
) / I
GATE
]
where I
GATE
is the average DH-high driver output-cur-
rent capability determined by:
I
GATE
= 2.5 / (R
DH
+ R
GATE
)
VV V V
V I ESR
V
V ESL
L ESL
V
I
Cf
I
VV
fL
V
V
RIPPLE RIPPLE ESR RIPPLE ESL RIPPLE C
RIPPLE ESR P P
RIPPLE ESL
IN
RIPPLE C
PP
OUT S
PP
IN OUT
S
OUT
IN
=++
=×
=
×
+
=
××
=
×
⎛
⎝
⎜
⎞
⎠
⎟
×
⎛
⎝
⎜
⎞
⎠
⎟
−
−
−
−
() () ()
()
()
()
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