Datasheet
MAX8520/MAX8521
6) To ensure high DC-loop gain and minimum loop
error, keep the board layout adjacent to the negative
input pin of the integrator (U2 in Figure1) clean and free
of moisture. Any contamination or leakage current into
this node can act to lower the DC gain of the integrator
which can degrade the accuracy of the thermal loop. If
space is available, it can also be helpful to surround the
negative input node of the integrator with a grounded
guard ring.
Refer to the MAX8520/MAX8521 evaluation kit for a
PCB layout example.
Chip Information
PROCESS: BiCMOS
Smallest TEC Power Drivers for Optical
Modules
16 ______________________________________________________________________________________
20
19
18
17
PVDD1
OS1
OS2
CS
16 PVDD2
13
12
11
14
15
V
DD
FREQ
PGND2
LX2
GND
4
3
2
1
COMP
SHDN
PGND1
LX1
5ITEC
6
7
8
9
MAXIM
MAXIP
MAXV
REF
10CTLI
MAX8520/
MAX8521
TOP VIEW
CONNECT EP TO GND
TQFN
+
EP
F6
PVDD2
LX2 LX2 LX1 LX1
PGND2 PGND2 PGND2 PGND1 PGND1 PGND1
OS2 FREQ GND2 GND2 COMP
SHDN
VDD GND2 GND2 ITEC
GND CTLI REF MAXV
MAX8521
MAXIP MAXIN
PVDD2 CS OS1 PVDD1 PVDD1
F5 F4 F3 F2 F1
E6 E5 E2 E1
D6 D5 D4 D3 D2 D1
C6 C5 C4 C3 C2 C1
B6 B5 B2 B1
A6 A5 A4 A3 A2 A1
+
UCSP/WLP
TOP VIEW
BUMPS ON BOTTOM
Pin Configurations
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
LAND
PATTERN NO.
20 TQFN-EP T2055+4
21-0140
90-0009
6 x 6 UCSP B36-2
21-0082
Refer to Application Note 1891
36 WLP W363A3+2
21-0024
Refer to Application Note 1891