Datasheet

MAX807L/M/N
Full-Featured µP Supervisory Circuit with
±1.5% Reset Accuracy
______________________________________________________________________________________ 11
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
OUT is actively pulled to the higher of V
CC
or V
BATT
. This
source turns off when the transmission gate is enabled.
Low-Line Comparator
The low-line comparator monitors V
CC
with a threshold
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
maskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system must
contend with a more rapid V
CC
fall time—such as when
the main battery is disconnected, a DC-DC converter
shuts down, or a high-side switch is opened during
normal operation—use capacitance on the V
CC
line to
provide time to execute the shutdown routine (Figure 9).
First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (V
LR(min)
),
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
C
HOLD
= (I
LOAD
x t
SHDN
) / V
LR
(min)
where t
SHDN
is the time required for the system to com-
plete the shutdown routine, and includes the V
CC
to
low-line propagation delay; and where I
LOAD
is the cur-
rent being drained from the capacitor, V
LR
is the low-
line to reset threshold.
V
CC
CE IN
RESET
THRESHOLD
CE OUT
RESET
RESET
26µs
28µs
26µs
MAX807
CE IN
50pF
C
LOAD
CE OUT
GND
V
RST
MAX
50Ω DRIVER
V
CC
Figure 7. Reset and Chip-Enable Timing Figure 8. CE Propagation Delay Test Circuit
GND
V
CC
TO µP NMI
C
HOLD
C
HOLD
> I
LOAD
x t
SHDN
V
LR
4.5V to 5.5V
LOW LINE
MAX807
REGULATOR
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP