Datasheet

brownout conditions. RESET is guaranteed to be a
logic low for 0V < V
CC
< V
RST
, provided V
BATT
is
greater than 1V. Without a backup battery (V
BATT
=
V
CC
= V
OUT
), RESET is guaranteed valid for V
CC
≥ 1V.
Once V
CC
exceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period
(t
RP
); after this interval, RESET becomes high imped-
ance (Figure 2). RESET is an open-drain output, and
requires a pullup resistor to V
CC
(Figure 3). Use a
4.7kΩ to 1MΩ pullup resistor that provides sufficient
current to assure the proper logic levels to the µP.
If a brownout condition occurs (V
CC
dips below the
reset threshold), RESET goes low. Each time RESET is
asserted, it stays low for the reset timeout period. Any
time V
CC
goes below the reset threshold, the internal
timer restarts.
The watchdog output (WDO) can also be used to initi-
ate a reset. See the Watchdog Output section.
The RESET output is the inverse of the RESET output,
and it can both source and sink current.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________ 9
V
CC
V
LOWLINE
(MAX793/MAX794)
V
RESET
(RESET PULLED UP TO V
CC
)
V
RESET
(MAX793/MAX794)
V
CE OUT
V
WDO
(MAX793/MAX794)
V
BOK
(MAX793)
V
PFO
(MAX793/MAX794)
SHOWN FOR V
CC
= 3.3V to 0V, V
BATT
= 3.6V, CE IN = GND, PFI = V
CC
.
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE
V
BATT ON
MAX794: V
RESET IN
= V
CC
(V
RST IN
/ V
RST
)
V
BATT
V
BATT
4µs
V
LL
V
RST
V
SW
20µs
20µs
25µs
10µs
25µs
25µs
25µs
25µs
Figure 2. Timing Diagram, V
CC
Falling