Datasheet

MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
8 _______________________________________________________________________________________
_______________Detailed Description
General Timing Characteristics
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the Selector Guide on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical V
CC
rise and fall times.
Manual Reset Input (MAX793/MAX794)
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
remains asserted while MR is low, and for t
RP
(200ms)
after it returns high. During the first half of the reset time-
out period (t
RP
), the state of MR is ignored if PFO is exter-
nally forced low to facilitate enabling the battery fresh-
ness seal. MR has an internal 70µA pullup current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec-
tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.
Reset Outputs
A microprocessor’s (µP’s) reset input starts the µP in a
known state. These MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code exe-
cution errors during power-up, power-down, and
V
LOWLINE
(MAX793/MAX794)
V
RESET
(PULLED UP TO V
CC
)
V
RESET
(MAX793/MAX794)
(PFO FOLLOWS PFI)
V
CE OUT
V
BATT
V
WDO
(MAX793/MAX794)
V
BOK
(MAX793)
MAX794: V
RESET IN
= V
CC
(V
RST IN
/ V
RST
)
PFO
(MAX793/MAX794)
BATT ON
SHOWN FOR V
CC
= 0V to 3.3V, V
BATT
= 3.6V, CE IN = GND.
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
5µs
V
SW
V
CC
V
RST
V
LL
t
RP
25µs
25µs
25µs
25µs
t
RP
t
RP
/
2
t
RP
/
2
Figure 1. Timing Diagram, V
CC
Rising