Datasheet

_______________Detailed Description
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator or test technician to initiate a
reset. The Manual Reset Input (MR) can be connected
directly to a switch, without an external pull-up resistor
or debouncing network. It connects to a 1.25V com-
parator, and has a pull-up to V
OUT
as shown in Figure
1. The propagation delay from asserting MR to RESET
asserted is 4µs typ. Pulsing MR low for a minimum of
15µs resets all the internal counters, sets the Watchdog
Output (WDO) and Watchdog-Pulse Output (WDPO)
high, and sets the Set Watchdog-Timeout (SWT) input
to V
OUT
- 0.6V, if it is not already connected to V
OUT
(for internal timeouts). It also disables the chip-enable
function, setting the Chip-Enable Output (CE OUT) to a
high state. The RESET output remains active as long as
MR is held low, and the reset-timeout period begins
after MR returns high (Figure 2).
Use this input as either a digital-logic input or a second
low-line comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
MAX791
Microprocessor Supervisory Circuit
8 _______________________________________________________________________________________
MAX791
CHIP-ENABLE
OUTPUT
CONTROL
V
CC
3
1
13
9
8
11
7
VBATT
CE IN
MR
SWT
WDI
PFI
RESET
GENERATION
TIMEBASE FOR
RESET AND
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
V
OUT
1.25V
GND
4
4.65V
150mV
10
LOWLINE
5
2
12
15
16
14
PFO
WDO
WDPO
RESET
CE OUT
6
V
OUT
BATT ON
Figure 1. MAX791 Block Diagram
MR
RESET
CE IN
0V
7.5µs TYP
15µs TYP
25µs MIN
CE OUT
Figure 2. Manual-Reset Timing Diagram
MAX791
*
*
OTHER
RESET
SOURCES
MANUAL RESET
MR
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" Connections Allow Multiple Reset Sources
to Connect to MR