Datasheet

Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 15’s circuit. When
the negative supply is valid, PFO is low. When the neg-
ative supply voltage drops, PFO goes high. This cir-
cuit’s accuracy is affected by the PFI threshold toler-
ance, the V
CC
voltage, and resistors R1 and R2.
Backup-Battery Replacement
The backup battery may be disconnected while V
CC
is
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
Negative-Going V
CC
Transients
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going V
CC
transients (glitches). It is usually undesirable to reset
the µP when V
CC
experiences only small glitches.
Figure 16 shows maximum transient duration vs. reset
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going V
CC
pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset com-
parator overdrive). The graph shows the maximum
pulse width that a negative-going V
CC
transient may
typically have without causing a reset pulse to be
issued. As the amplitude of the transient increases (i.e.,
goes farther below the reset threshold), the maximum
allowable pulse width decreases. Typically, a V
CC
tran-
sient that goes 100mV below the reset threshold and
lasts for 40µs or less will not cause a reset pulse to be
issued.
A 100nF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
Connecting a Timing Capacitor to SWT
SWT is internally connected to a ±100nA current
source. When a capacitor is connected from SWT to
ground (to select an alternative watchdog-timeout peri-
od), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
watchdog-timeout period. To prevent timing errors or
oscillator start-up problems, minimize external current
leakage sources at this pin, and locate the capacitor as
MAX791
Microprocessor Supervisory Circuit
______________________________________________________________________________________ 15
MAX791
V
CC
GND
PFI
*OPTIONAL
R2
R3
R1
V
IN
+5V
C1*
TO µP
PFO
V
TRIP
= 1.25
R1 + R2
R2
V
H
= 1.25 /
R2
|| R3
VL - 1.25
+
5 - 1.25
=
1.25
R1 + R2
||
R3 R1 R3 R2
PFO
+5V
0V
0V V
H
V
TRIP
V
IN
V
L
Figure 14. Adding Hysteresis to the Power-Fail Comparator
MAX791
V
OUT
GND
CE IN
CE
CE
CE OUT
CE
CE
CE
CE
CE
CE
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMs.
MINIMUM Rp VALUE IS 1kΩ
ACTIVE-HIGH CE
LINES FROM LOGIC
RAM 1
RAM 2
RAM 3
RAM 4
Rp*
Figure 13. Alternate CE Gating