Datasheet

MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25NC.) (Notes 2, 3)
Note 2:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 3: All digital inputs at V
CC
or GND.
Note 4: Guaranteed by design.
Note 5: C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 7: I
SINK
= 6mA. C
B
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.8V and 2.1V.
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I
2
C TIMING SPECIFICATIONS
SCL Serial-Clock Frequency f
SCL
Bus timeout enabled 0.05 400
kHz
Bus timeout disabled 0 400
Bus Free Time Between a STOP and
START Condition
t
BUF
1.3
Fs
Hold Time (Repeated) START Condition t
HD, STA
0.6
Fs
Repeated START Condition Setup Time t
SU, STA
0.6
Fs
STOP Condition Setup Time t
SU, STO
0.6
Fs
Data Hold Time t
HD, DAT
(Note 6) 0.9
Fs
Data Setup Time t
SU, DAT
100 ns
SCL Clock Low Period t
LOW
1.3
Fs
SCL Clock High Period t
HIGH
0.7
Fs
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
(Notes 4, 5)
20 +
0.1C
B
300 ns
Fall Time of Both SDA and SCL Signals,
Receiving
t
F
(Notes 4, 5)
20 +
0.1C
B
300 ns
Fall Time of SDA Signal, Transmitting t
F, TX
(Notes 4, 7)
20 +
0.1C
B
250 ns
Pulse Width of Spike Suppressed t
SP
(Notes 4, 8) 50 ns
Capacitive Load for Each Bus Line C
B
(Note 4) 400 pF
Bus Time Out t
TIMEOUT
14 19 27 ms
ESD PROTECTION
ROW7–ROW0, COL7–COL0
IEC 61000-4-2 Air-Gap Discharge
Q15
kV
IEC 61000-4-2 Contact Discharge
Q8
All Other Pins Human Body Model
Q2.5
kV