Datasheet

MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
19Maxim Integrated
Switch On-Resistance
The device is designed to be insensitive to resistance,
either in the key switches, or the switch routing to and
from the appropriate COL_ and ROW_ up to 5kI (max).
These controllers are therefore compatible with low-cost
membrane and conductive carbon switches.
Hot Insertion
The INT, SCL, and AD0 inputs and SDA remain high
impedance with up to 5.5V asserted on them when the
device powers down (V
CC
= 0V). I/O ports remain high
impedance with up to 5.5V asserted on them when not
powered. Use the device in hot-swap applications.
Staggered PWM
The LED’s on-time in each PWM cycle is phase delayed by
45N into four evenly spaced start positions. Optimize phas-
ing, when using fewer than four ports as constant-current
outputs, by allocating the ports with the most appropriate
start positions. For example, if using two constant-current
outputs, choose COL4 and COL6 because their PWM
start positions are evenly spaced. In general, choose
the ports that spread the current demand from the ports’
load supply.
Power-Supply Considerations
The device operates with a 1.62V to 3.6V power-supply
voltage. Bypass the power supply (V
CC
) to GND with a
0.1µF or higher ceramic capacitor as close as possible
to the device. Bypass the logic power supply (V
LA
) to
GND with a 0.1µF or higher ceramic capacitor as close
as possible to the device.
ESD Protection
All the device pins meet the ±2.5kV Human Body Model
ESD tolerances. Key-switch inputs and GPIOs meet IEC
61000-4-2 ESD protection. The IEC test stresses consist
of 10 consecutive ESD discharges per polarity at the
maximum specified level and below (per IEC 61000-4-2).
Test criteria include:
• ThepowereddevicedoesnotlatchupduringtheESD
discharge event.
• The device subsequently passes the final test used
for prescreening.
Tables 5 and 6 are taken from the IEC 61000-4-2:
Edition 1.1 1999-05: Electromagnetic compatibility (EMC)
Testing and measurement techniques—Electrostatic dis-
charge immunity test.
Table 5. ESD Test Levels
Table 6. ESD Waveform Parameters
X = Open level. The level has to be specified in the dedicated
equipment specification. If higher voltages than those shown
are specified, special test equipment might be needed.
1A—CONTACT DISCHARGE 1B—AIR DISCHARGE
LEVEL
TEST VOLTAGE
(kV)
LEVEL
TEST
VOLTAGE (kV)
1 2 1 2
2 4 2 4
3 6 3 8
4 8 4 15
X Special X Special
LEVEL
INDICATED
VOLTAGE
(kV)
FIRST PEAK
OF CURRENT
DISCHARGE Q10%
(A)
RISE TIME (t
r
) WITH
DISCHARGE SWITCH
(ns)
CURRENT
(Q30%) AT 30ns
(A)
CURRENT (Q30%)
AT 60ns
(A)
1 2 7.5 0.7 to 1 4 2
2 4 15 0.7 to 1 8 4
3 6 22.5 0.7 to 1 12 6
4 8 30 0.7 to 1 16 8