Datasheet

MAX7370
8 x 8 Key-Switch Controller and LED Driver/GPIOs
with I2C Interface and High Level of ESD Protection
13Maxim Integrated
COL4–COL7 LED Configuration
Registers (0x54 to 0x57)
Registers 0x54 to 0x57 set individual configurations for
each port. See Table 30. D5 sets the port’s PWM setting
to either the common or individual PWM setting. Bits
D[4:2] enable and set the port’s individual blink period
from 0 to 4096ms. Bits D[1:0] set a port’s blink duty cycle.
Interrupt Mask 1 and 2 Registers (0x58, 0x59)
The Interrupt Mask 1 and 2 registers control which ports
trigger an interrupt for ROW7–ROW0 and COL7–COL0,
respectively. See Tables 31 and 32. Set the bit to 0 to
enable the interrupt. Set the bit to 1 to mask the interrupt.
If the port that has generated the interrupt is not masked,
the interrupt causes the INT signal to assert. A read of the
GPIO Values 1 and 2 registers (0x3A, 0x3B) is required
to deassert the INT pin. Note that transitions that occur
while the INT signal is asserted, but before the read of the
GPIO Values 1 and 2 registers, set the appropriate bit of
the GPIO Values 1 and 2 registers only, but has no effect
on the INT pin as it is already asserted. However, transi-
tions that occur when the I
2
C is active cannot be latched
into the GPIO Values 1 and 2 registers until after the read
has taken place. If there are transitions that cause the
INT signal to assert, during the time of an I
2
C read, they
cause the INT signal to reassert once the read transac-
tion has taken place. Note that the interrupt configura-
tions only apply when a port is configured as an input.
GPI Trigger Mode 1 and 2 Registers (0x5A, 0x5B)
The GPI Trigger Mode 1 and 2 registers control how ports
can trigger an interrupt for ROW7–ROW0 and COL7–
COL0, respectively. See Tables 33 and 34. Set the bit to
0 for rising-edge triggering. Set the bit to 1 for rising- and
falling-edge triggering.
The inputs are debounced (if enabled) by taking a snap-
shot of the port state when the transition occurs, and
another after the debounce time has elapsed—ensuring
that the state of the port is stable prior to triggering the
interrupt. After the debounce cycle, an interrupt is gener-
ated and the INT pin asserted if it is not masked for that
particular port. Regardless of whether or not the INT sig-
nal is masked, the GPIO Values 1 and 2 registers (0x3A,
0x3B) report the state of all input ports.
Sleep Mode
The device is put into sleep mode by clearing bit D7 in
the Configuration register, or after power-on reset (POR).
In sleep mode, the keyscan controller is disabled and the
device draws minimal current. No additional supply cur-
rent is drawn if no keys are pressed. All switch-matrix cur-
rent sources are turned off, and row outputs ROW7–ROW0
are low and column outputs COL7–COL0 become high.
The device is taken out of sleep mode and put into oper-
ating mode by setting bit D7 in the configuration register.
The keyscan controller FIFO buffers are cleared and key
monitoring starts. Note that rewriting the configuration
register with bit D7 high, when bit D7 was already high,
does not clear the FIFOs. The FIFOs are only cleared
when the device is changing state from sleep mode to
operating mode.
In sleep mode, the internal oscillator is disabled and
I
2
C timeout features are disabled. The GPO or LED
ports consume current even in sleep mode. The part
does not enter sleep mode if any of the GPIOs or LED
drivers are enabled.
LED Fade
Set the fade cycle time in the GPIO Global Configuration
register (0x40) to a non-zero value to enable fade in/out.
See Table 24. Fade in increases an LED’s PWM intensity
in 16 even steps, from zero to its stored value. Fade out
decreases an LED’s PWM intensity in 16 even steps from
its current value to zero. Fading occurs automatically in
any of the following scenarios:
• Change the common PWM register value from any
value to zero to cause all ports using the common
PWM register settings to fade out. No ports using
individual PWM settings are affected.
• ChangethecommonPWMregistervaluetoanyvalue
from zero to cause all ports using the common PWM
register settings to fade in. No ports using individual
PWM settings are affected.
• Take thepartoutof sleepmodetocauseall portsto
fade in. Changing an individual PWM intensity dur-
ing fade in automatically cancels that port’s fade and
immediately outputs at its newly programmed intensity.