Datasheet

MAX7367/MAX7368/MAX7369
4-Channel I
2
C Switches/Multiplexer
_______________________________________________________________________________________ 5
Note 1: All parameters are production tested at T
A
= +25°C and guaranteed by design over the specified temperature range.
Note 2: Minimum value is not production tested. Guaranteed by design.
Note 3: Pass gate propagation delay is calculated from 20Ω (typ) R
ON
and the 15pF load capacitance. Not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to the V
IL
of the SCL) in order to
bridge the undefined region of SCL’s falling edge.
Note 5: C
b
= total capacitance of one bus line in pF.
Note 6: Guaranteed by design.
Note 7: Measurements taken with a 1kΩ pullup resistor and 50pF load.
TIMING CHARACTERISTICS (Figure 1) (continued)
(V
DD
= 2.3V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
f
SCL
= 100kHz 300
Fall Time of Both SDA and SCL
Signals
t
f
f
SCL
= 400kHz (Note 5)
20 +
0.1C
b
300
ns
Capacitive Load for Each Bus Line C
b
(Note 6) 400 pF
Pulse Width of Spikes Suppressed t
SP
50 ns
Data Valid Time from High to Low t
VD
;
DATL
(Note 7) 1 µs
Data Valid Time from Low to High t
VD
;
DATH
(Note 7) 0.6 µs
Data Valid Acknowledge t
VD
;
ACK
1µs
INT (Figure 2)
INT_ to INT Active Valid Time t
IV
4µs
INT_ to INT Inactive Delay Time t
IR
2µs
Low-Level, Pulse-Width Rejection
or INT_ Inputs
t
W
(
REJ
)
L
1µs
High-Level, Pulse-Width Rejection
or INT_ Inputs
t
W
(
REJ
)
H
0.5 µs
RESET (Figure 3)
Pulse-Width Low Reset t
WL
(
RST
)
4ns
Reset Time (SDA Clear) t
RST
500 ns
Recovery to Start t
REC
;
STA
0ns
SDA
SCL
t
BUF
t
SU;STO
t
r
t
SP
t
HD;STA
t
SU;STA
t
f
t
HIGH
t
SU;DAT
t
HD;DAT
t
r
t
LOW
t
HD;STA
t
f
S S
S
r
P
Figure 1. 2-Wire Serial-Interface Timing Diagram