Datasheet
MAX7325
I
2
C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
13
Maxim Integrated
SCL
MAX7325 SLAVE ADDRESSS110
A
P
1
PORTS
INT OUTPUT
R/W
PORT SNAPSHOT
t
IV
t
PH
t
IR
AD0D1D2D3D4D5D6D7
PORT SNAPSHOT
t
PSU
t
IP
D7 D6 D5 D4 D3 D2 D1 D0 N
PORT SNAPSHOT
INT REMAINS HIGH UNTIL STOP CONDITION
I0
I1
I2I3I4I5
I6
I7
F0
F1
F2F3F4F5
F6
F7
PORT INPUTS INTERRUPT FLAGS
S = START CONDITION SHADED = SLAVE TRANSMISSION
P = STOP CONDITION N = NOT ACKNOWLEDGE
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM MAX7325
Figure 7. Reading Open-Drain Ports of the MAX7325 (2 Data Bytes)
SCL
MAX7325 SLAVE ADDRESS
SA
P
1
ACKNOWLEDGE FROM MAX7325
PORT SNAPSHOT DATA
PORT SNAPSHOT TAKEN
A
P0P1P2P3
DATA 1
P4P5P6P7
D0D1D2D3D4D5D6D7
PORT SNAPSHOT TAKEN
ACKNOWLEDGE
FROM MASTER
R/W
Figure 8. Reading Push-Pull Ports of MAX7325
acknowledge. The new snapshot data is the current
port data transmitted to the master, and therefore, port
changes occuring during the transmission are detect-
ed. INT remains high until the STOP condition.
The master can read 2 bytes from the open-drain ports
of the MAX7325 and subsequently issues a STOP con-
dition (Figure 7). In this case, the MAX7325 transmits
the current port data, followed by the change flags. The
change flags are then cleared, and transition detection
is reset. INT goes high (high impedance if an external
pullup resistor is not fitted) during the slave acknowl-
edge. The new snapshot data is the current port data
transmitted to the master, and therefore, port changes
occuring during the transmission are detected. INT
remains high until the STOP condition.
A read from the push-pull ports of the MAX7325 starts
with the master transmitting the group’s slave address
with the R/W bit set high. The MAX7325 acknowledges
the slave address, and samples the logic state of the
output ports during the acknowledge bit. The master can
read one or more bytes from the push-pull ports of the
MAX7325 and then issues a STOP condition (Figure 8).
The MAX7325 transmits the current port data, read
back from the actual port outputs (not the port output
latches) during the acknowledge. If a port is forced to a
logic state other than its programmed state, the read-
back reflects this. If driving a capacitive load, the read-
back port level verification algorithms may need to take
the RC rise/fall time into account.