Datasheet

Serial Interface
Serial Addressing
The MAX7321 operates as a slave that sends and
receives data through an I
2
C interface. The interface uses
a serial-data line (SDA) and a serial-clock line (SCL) to
achieve bidirectional communication between master(s)
and slave(s). The master initiates all data transfers to
and from the MAX7321 and generates the SCL clock that
synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain output.
A pullup resistor, typically 4.7kΩ, is required on SDA.
SCL operates only as an input. A pullup resistor, typically
4.7kΩ, is required on SCL if there are multiple masters
on the 2-wire interface, or if the master in a single-master
system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7321’s 7-bit slave address
plus R/W bit, 1 or more data bytes, and finally a STOP
condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, the master issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission
(Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient uses
to acknowledge receipt of each byte of data (Figure 4).
Each byte transferred effectively requires 9 bits. The
master generates the 9th clock pulse, and the recipient
pulls down SDA during the acknowledge clock pulse,
such that the SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
MAX7321, the MAX7321 generates the acknowledge bit
because the device is the recipient. When the MAX7321
is transmitting to the master, the master generates the
acknowledge bit because the master is the recipient.
Slave Address
The MAX7321 has a 7-bit-long slave address (Figure 5).
The eighth bit following the 7-bit slave address is the R/W
bit. It is low for a write command, and high for a read
command.
The first (A6), second (A5), and third (A4) bits of the
MAX7321 slave address are always 1, 1, and 0.
Connect AD2 and AD0 to GND, V+, SDA, or SCL to
select slave address bits A3, A2, A1, and A0. The
MAX7321 has 16 possible slave addresses (Table 3),
allowing up to 16 MAX7321 devices on an I
2
C bus.
Figure 2. START and STOP Conditions
Figure 1. 2-Wire Serial Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
S P
SCL
SDA
t
R
t
F
t
BUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
t
SU,STO
t
HD,STA
t
SU,STA
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
HD,STA
www.maximintegrated.com
Maxim Integrated │ 9
MAX7321 I
2
C Port Expander with 8 Open-Drain I/Os