Datasheet

Writing to the MAX7321
A write to the MAX7321 starts with the master transmit-
ting the MAX7321’s slave address with the R/W bit set
low. The MAX7321 acknowledges the slave address, and
samples the ports (takes a snapshot) during acknowl-
edge. INT goes high (high impedance if an external
pullup resistor is not fitted) during the slave acknowledge.
Typically, the master proceeds to transmit 1 or more bytes
of data. The MAX7321 acknowledges these subsequent
bytes of data and updates the I/O ports with each new
byte until the master issues a STOP condition (Figure 8).
Applications Information
Port Input and I2C Interface Level
Translation from Higher or Lower
Logic Voltages
The MAX7321’s SDA, SCL, AD0, AD2, RST, INT, and
I/O ports P0–P7 are overvoltage protected to +6V inde-
pendent of V+. This allows the MAX7321 to operate from
a lower supply voltage, such as +3.3V, while the I
2
C
interface and/or any of the eight I/O ports are driven as
inputs driven from a higher logic level, such as +5V.
The MAX7321 can operate from a higher supply volt-
age, such as +3V, while the I
2
C interface and/or some
of the I/O ports (P0–P7) are driven from a lower logic
level, such as +2.5V. Apply a minimum voltage of
0.7 x V+ to assert a logic-high on any I/O port (e.g.,
a MAX7321 operating from a +5V supply may not
recognize a +3.3V nominal logic-high). One solution for
input-level translation is to drive MAX7321 I/Os from
open-drain outputs. Use a pullup resistor to V+ or a
higher supply to ensure a high logic voltage greater
than 0.7 x V+.
Port-Output Port-Level Translation
The open-drain output architecture allows for level
translation to higher or lower voltages than the
MAX7321’s supply. Use an external pullup resistor on
any output to convert the high-impedance logic-high
condition to a positive voltage level. The resistor can be
connected to any voltage up to +6V, and the resistor
value chosen to ensure no more than 20mA is sunk in
the logic-low condition. For interfacing CMOS inputs, a
pullup resistor value of 220kΩ is a good starting point.
Use a lower resistance to improve noise immunity, in
applications where power consumption is less critical,
or where a faster rise time is needed for a given capac-
itive load.
Each of the I/O ports (P0–P7) has a protection diode to
GND (Figure 9). When a port is driven to a voltage lower
than GND, the protection diode clamps the voltage to a
diode drop below GND.
Each of the P0–P7 I/O ports also has a 40kΩ (typ) pullup
resistor that can be enabled or disabled. When a port
is driven to a voltage higher than V+, the body diode of
the pullup enable switch conducts and the 40kΩ pullup
resistor is enabled. When the MAX7321 is powered
down (V+ = 0), each I/O port appears as a 40kΩ resistor
in series with a diode connected to zero. I/O ports are
protected to +6V under any of these circumstances
(Figure 9).
Figure 8. Writing to the MAX7321
SCL
SDA
START CONDITION R/W
SLAVE ADDRESS
S 0
1 2 3 4 5 6 7 8
A A A
t
PV
DATA 1 DATA 2
t
PV
DATA TO PORT DATA TO PORT
t
PV
DATA 2 VALIDDATA 1 VALID
INTERNAL WRITE
TO PORT
DATA OUT
FROM PORT
t
PV
S = START CONDITION SHADED = SLAVE TRANSMISSION
P = STOP CONDITION N = NOT ACKNOWLEDGE
www.maximintegrated.com
Maxim Integrated │ 12
MAX7321 I
2
C Port Expander with 8 Open-Drain I/Os