Datasheet

The RST input clears the serial interface in case of a
hung bus, terminating any serial transaction to or from
the MAX7320.
When the MAX7320 is read through the serial interface,
the actual logic states at the ports are read back.
Output port power-up logic states are selected by the
address select inputs AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Table 3).
RST Input
The RST input voids any I
2
C transaction involving the
MAX7320 and forces the MAX7320 into the I
2
C STOP
condition. A reset does not change the contents of the
output register. RST is overvoltage tolerant to +5.5V.
Standby Mode
When the serial interface is idle, the MAX7320 automat-
ically enters standby mode, drawing minimal supply
current.
Slave Address and Power-Up
Default Logic States
Address inputs AD0 and AD2 determine the MAX7320
slave address and set the power-up output logic states.
Power-up logic states are set in groups of four (see
Table 3). The MAX7320 uses a different range of slave
addresses (101xxxx) than the MAX7319, MAX7321,
MAX7322, and MAX7323 (110xxxx).
The MAX7320 slave address is determined on each I
2
C
transmission, regardless of whether the transmission is
actually addressing the MAX7320. The MAX7320 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. This means that the
MAX7320 slave address can be configured dynamical-
ly in the application without cycling the device supply.
On initial power-up, the MAX7320 cannot decode the
address inputs AD0 and AD2 fully until the first I
2
C
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection determines the power-up logic levels
of the output ports. However, at power-up, the I
2
C SDA
and SCL bus interface lines are high impedance at the
pins of every device (master or slave) connected to the
bus, including the MAX7320. This is guaranteed as part
of the I
2
C specification. Therefore, address inputs AD0
and AD2 that are connected to SDA or SCL normally
appear at power-up to be connected to V+. The power-
up output state selection logic uses AD0 to select the
power-up state for ports O3–O0, and uses AD2 to
select the power-up state for ports O7–O4. The rule is
that a logic-high, SDA, or SCL connection selects a
MAX7320
I
2
C Port Expander with Eight Push-Pull Outputs
_______________________________________________________________________________________ 7
PIN
CONNECTION
DEVICE ADDRESS OUTPUTS POWER-UP DEFAULT
AD2 AD0 A6 A5 A4 A3 A2 A1 A0 O7 O6 O5 O4 O3 O2 O1 O0
SCLGND101000011110000
SCLV+101000111111111
SCLSCL101001011111111
SCLSDA101001111111111
SDAGND101010011110000
SDAV+101010111111111
SDASCL101011011111111
SDASDA101011111111111
GNDGND101100000000000
GND V+ 1 0 1100100001111
GNDSCL101101000001111
GNDSDA101101100001111
V+GND101110011110000
V+V+101110111111111
V+SCL101111011111111
V+SDA101111111111111
Table 3. MAX7320 Address Map