Datasheet

Table 2. Initial Power-Up Register Status
Table 1. Register Address Map
REGISTER POWER-UP CONDITION
ADDRESS
CODE (hex)
REGISTER DATA
D7 D6 D5 D4 D3 D2 D1 D0
Port P0 output level Port 0 high impedance 0x00 1 1 1 1 1 1 1 1
Port P1 output level Port 1 high impedance 0x01 1 1 1 1 1 1 1 1
Port P2 output level Port 2 high impedance 0x02 1 1 1 1 1 1 1 1
Port P3 output level Port 3 high impedance 0x03 1 1 1 1 1 1 1 1
Port P4 output level Port 4 high impedance 0x04 1 1 1 1 1 1 1 1
Port P5 output level Port 5 high impedance 0x05 1 1 1 1 1 1 1 1
Port P6 output level Port 6 high impedance 0x06 1 1 1 1 1 1 1 1
Port P7 output level Port 7 high impedance 0x07 1 1 1 1 1 1 1 1
Port P8 output level Port 8 high impedance 0x08 1 1 1 1 1 1 1 1
Port P9 output level Port 9 high impedance 0x09 1 1 1 1 1 1 1 1
RAM 0x00 0x13 0 0 0 0 0 0 0 0
REGISTER
COMMAND ADDRESS
CODE
(hex)
D15 D14 D13 D12 D11 D10 D9 D8
Port P0 output level R/W 0 0 0 0 0 0 0 0x00
Port P1 output level R/W 0 0 0 0 0 0 1 0x01
Port P2 output level R/W 0 0 0 0 0 1 0 0x02
Port P3 output level R/W 0 0 0 0 0 1 1 0x03
Port P4 output level R/W 0 0 0 0 1 0 0 0x04
Port P5 output level R/W 0 0 0 0 1 0 1 0x05
Port P6 output level R/W 0 0 0 0 1 1 0 0x06
Port P7 output level R/W 0 0 0 0 1 1 1 0x07
Port P8 output level R/W 0 0 0 1 0 0 0 0x08
Port P9 output level R/W 0 0 0 1 0 0 1 0x09
Write ports P0 through P9 with same output level 0
0 0 0 1 0 1 0 0x0A
Read port P0 output level 1
Write ports P0 through P3 with same output level 0
0 0 0 1 0 1 1 0x0B
Read port P0 output level 1
Write ports P4 through P7 with same output level 0
0 0 0 1 1 0 0 0x0C
Read port P4 output level 1
Write ports P8 or P9 with same output level 0
0 0 0 1 1 0 1 0x0D
Read port P8 output level 1
Read ports P7 through P0 inputs 1 0 0 0 1 1 1 0 0x0E
Read ports P9 and P8 inputs 1 0 0 0 1 1 1 1 0x0F
RAM R/W 0 0 1 0 0 1 1 0x13
No-op R/W 0 1 0 0 0 0 0 0x20
Factory reserved; do not write to this register R/W 1 1 1 1 1 0 1 0x7D
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Maxim Integrated │ 6
MAX7317 10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection