Datasheet

Applications Information
Hot Insertion
The I/O ports P0–P9 remain high impedance with up to
8V asserted on them when the MAX7317 is powered
down (V+ = 0V). The MAX7317 can therefore be used in
hot-swap applications.
SPI Routing Considerations
The MAX7317’s SPI interface is guaranteed to
operate at 26Mbps on a 2.5V supply, and on a 3.3V
supply typically operates at 35Mbps. This means that
transmission line issues should be considered when
the interface connections are longer than 100mm,
particularly with higher supply voltages. Avoid running
long adjacent tracks for SCLK, DIN, and CS without
interleaving GND traces; otherwise, the signals may
cross-couple, giving false clock or chip-select transi-
tions. Ringing may manifest itself as communication
issues, often intermittent, typically due to double clocking
caused by ringing at the SCLK input. Fit a 1kΩ to 10kΩ
parallel termination resistor to either GND or V+ at the
DIN, SCLK, and CS inputs to damp ringing for moder-
ately long interface runs. Use line-impedance-matching
terminations when making connections between boards.
Output-Level Translation
The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
than the MAX7317 supply. An external pullup resistor
can be used on any output to convert the high-
imped-ance logic-high condition to a positive voltage level.
The resistor can be connected to any voltage up to
7V. When using a pullup on a constant-current output,
select the resistor value to sink no more than a few
hundred µA in logic-low condition. This ensures that the
current sink output saturates close to GND. For
interfacing CMOS inputs, a pullup resistor value of 220kΩ
is a good starting point. Use a lower resistance to
improve noise immunity in applications where power
consumption is less critical, or where a faster rise time is
needed for a given capacitive load.
Power-Supply Considerations
The MAX7317 operates with a power-supply voltage of
2.25V to 3.6V. Bypass the power supply to GND with
a 0.047µF ceramic capacitor as close to the device as
possible. For the QFN version, connect the underside
exposed pad to GND.
Figure 6. Transmission of More than 16 Bits to the MAX7317
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
16 QSOP E16+4 21-0055 90-0167
16 TQFN-EP T1633+4 21-0136 90-0031
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SCLK
V+
DIN
DOUT
P9
P8
P7
P6
P5
TOP VIEW
MAX7317AEE
QSOP
CS
P0
P3
P1
P2
P4
GND
.
N-15
N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16
BIT
1
BIT
2
N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
CS
SCLK
DIN
DOUT
www.maximintegrated.com
Maxim Integrated │ 10
MAX7317 10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Pin Congurations (continued)
Chip Information
TRANSISTOR COUNT: 14,865
PROCESS: BiCMOS