Datasheet

MAX7310
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Reads from the output port register reflect the
value that is in the flip-flop controlling the output selec-
tion, not the actual I/O value, which may differ if the out-
put is overloaded.
The polarity inversion register enables polarity inversion
of ports defined as inputs by the configuration register.
Set the bit in the polarity inversion register (write with a
1) to invert the corresponding port pin’s polarity. Clear
the bit in the polarity inversion register (write with a
zero) to retain the corresponding port pin’s original
polarity.
The configuration register configures the directions of
the ports. Set the bit in the configuration register to
enable the corresponding port pin as an input with a
high-impedance output driver. Clear the bit in the con-
figuration register to enable the corresponding port pin
as an output.
Set bit T0 to enable the bus timeout function and low to
disable the bus timeout function. Enabling the timeout
feature resets the serial bus interface when SCL stops
either high or low during a read or write access to the
MAX7310. If either SCL or SDA is low for more than
30ms min and 60ms max after the start of a valid serial
transfer, the interface resets itself. Resetting the serial
bus interface sets up SDA as an input. The MAX7310
then waits for another start condition.
Standby
The MAX7310 goes into standby when all pins are set
to V+ or GND. Standby supply current is typically
1.7µA.
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
8 _______________________________________________________________________________________
Table 3. Register 1—Output Port Register
BIT O7 O6 O5 O4 O3 O2 O1 O0
Default 0 0 0 0 0 0 0 0
Table 4. Register 2—Polarity Inversion Register
BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Default 1 1 1 10000
Table 5. Register 3—Configuration Register
BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Default 1 1 1 11111
Table 6. Register 4—Timeout Register
BIT T7 T6 T5 T4 T3 T2 T1 T0
Default x x x x x x x 1
Table 1. Register Address
REGISTER
ADDRESS
(hex)
FUNCTION PROTOCOL
0x00 Input port register Read byte.
0x01 Output port register Read/write byte.
0x02
Polarity inversion
register
Read/write byte.
0x03
Configuration
register
Read/write byte.
0x04 Timeout register Read/write byte.
0xFF Reserved register
Factory reserved.
Do not write to this
register.
Table 2. Register 0—Input Port Register
BIT I7 I6 I5 I4 I3 I2 I1 I0