Datasheet

MAX7310
2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
_______________________________________________________________________________________ 3
Note 1: All parameters are 100% production tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a 30ms minimum.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IL
of the SCL signal) in
order to bridge the undefined region of SCL’s falling edge.
Note 4: t
F
measured between 90% to 10% of V+.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
Leakage Current -1 +1 µA
Input Capacitance 10 pF
AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T
A
= -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
SCL
(Note 2) 400 kHz
BUS Timeout t
TIMEOUT
30 60 ms
Bus Free Time Between STOP
and START Condition
t
BUF
Figure 2 1.3 µs
Hold Time (Repeated) START
Condition
t
HD
,
STA
Figure 2 0.6 µs
Repeated START Condition Setup
Time
t
SU
,
STA
Figure 2 0.6 µs
STOP Condition Setup Time t
SU
,
STO
Figure 2 0.6 µs
Data Hold Time t
HD
,
DAT
Figure 2 (Note 3) 0.9 µs
Data Setup Time t
SU
,
DAT
Figure 2 0.1 µs
SCL Low Period t
LOW
Figure 2 1.3 µs
SCL High Period t
HIGH
Figure 2 0.7 µs
SCL/SDA Fall Time (Transmitting) t
F
Figure 2 (Note 4) 250 ns
Pulse Width of Spike Supressed t
SP
(Note 5) 50 ns
PORT TIMING
Output Data Valid t
PV
Figure 9 1 µs
Input Data Setup Time t
PS
Figure 10 29 µs
Input Data Hold Time t
PH
Figure 10 0 µs
RESET
Reset Pulse Width 100 ns