Datasheet

Figure 10. Maskable GPIO Ports P24 to P31
GPIO INPUT
CONDITIONING
P31
P30
P29
P28
P27
P26
P25
P24
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
OR
CONFIGURATION REGISTER M BIT = 1
R
S
GPIO IN
GPIO/PORT OUT
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
INT STATUS STORED AS MSB OF MASK REGISTER
MASK REGISTER BIT 6
MASK REGISTER BIT 5
MASK REGISTER BIT 4
MASK REGISTER BIT 3
MASK REGISTER BIT 2
MASK REGISTER BIT 1
MASK REGISTER LSB
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
GPIO INPUT
CONDITIONING
GPIO/PORT
OUTPUT LATCH
INT
OUTPUT LATCH
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Maxim Integrated │ 17
MAX7300 2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander