Datasheet

MAX71020
Single-Chip Electricity Meter AFE
25Maxim Integrated
Table 8. Hardware Control Register Map (continued)
*Default values given for standard CE code (2520 sample frequency, gain = 9).
NAME
BYTE
ADDRESS
R/W
DEFAULT
VALUE*
DESCRIPTION
INT_CFG 0x30F R/W
0x0000
8000
Interrupt configuration register: configure the behavior of the INTZ pin.
BIT NAME DESCRIPTION
0 IE_WPULSE
Enables an interrupt to occur on the leading edge of
WPULSE
1 IE_VPULSE
Enables an interrupt to occur on the leading edge of
VPULSE
2 IE_YPULSE
Enables an interrupt to occur on the leading edge of
YPULSE
3 IE_XPULSE
Enables an interrupt to occur on the leading edge of
XPULSE
4 IE_XDATA
Enables an interrupt to occur at the conclusion of the
accumulation interval, indicating that fresh data is
available
5 IE_CEBUSY
Enables an interrupt to occur when the CE cycles is
complete
6 Reserved —
7 IE_VSTAT
Enables an interrupt to occur when the VSYS status
changes
11:8 INT_POL
Interrupt polarity for the PULSE edges. The default
polarity is falling edge.
INT_POL[3]=1: Interrupt on rising edge of YPULSE
INT_POL[2]=1: Interrupt on rising edge of XPULSE
INT_POL[1]=1: Interrupt on rising edge of VPULSE
INT_POL[0]=1: Interrupt on rising edge of WPULSE
14:12 Reserved —
15 D_ODINTZ
Enable open-drain on the INTZ output. By default, the
pin is configured as a CMOS totem-pole output.
31:16 Reserved —