Datasheet

MAX71020
Single-Chip Electricity Meter AFE
19Maxim Integrated
Host connections include the INTZ pin, the RESETZ pin,
and an optional YPULSE pin. In the host controller, the
DIO pin connected to INTZ should generate an interrupt.
This interrupt signals to the host that an accumulation
cycle has been completed.
Metrology Temperature Compensation
Voltage Reference Precision
Since the VREF bandgap amplifier is chopper-stabilized
the DC offset voltage, which is the most significant long-
term drift mechanism in the voltage references, is automati-
cally removed by the chopper circuit. Maxim Integrated
trims the VREF voltage reference during the device manu-
facturing process to ensure the best possible accuracy.
The reference voltage (VREF) is trimmed to a target
value of 1.205V nominal. During this trimming process,
the TRIMT[7:0] value is stored in nonvolatile fuses.
TRIMT[7:0] is trimmed to a value that results in minimum
VREF variation with temperature.
The TRIMT[7:0] value can be read by the host controller
during initialization to calculate parabolic temperature
compensation coefficients suitable for each individual
device. The achievable temperature coefficient for VREF
is ±40ppm/°C.
Considering the factory calibration temperature of VREF
to be +22°C and the industrial temperature range (-40°C
to +85°C), the VREF error at temperature extremes can
be calculated as:
(85°C - 22°C) x 40ppm/°C = +2520ppm = ±0.252%
and
(-40°C - 22°C) x 40ppm/°C = +2480ppm = -0.248%
The above calculation implies that both the voltage and
the current measurements are individually subject to a
theoretical maximum error of approximately ±0.25%.
When the voltage sample and current sample are multi-
plied together to obtain the energy per multiplexer frame,
the voltage error and current error combine resulting in
approximately ±0.5% maximum energy measurement
error. However, this theoretical ±0.5% error considers
only the voltage reference (VREF) as an error source.
In practice, other error sources exist in the system. The
principal remaining error sources are the current sensors
(shunts or CTs) and their corresponding signal condition-
ing circuits, and the resistor voltage-divider used to mea-
sure the voltage. The MAX71020 0.5% grade devices
should be used in class 1% designs, allowing sufficient
margin for the other error sources in the system.
Mechanism
The MAX71020’s CE code performs temperature com-
pensation for the metrology when the EXT_TEMP bit in
the CECONFIG register is 0 (default setting). In the inter-
nal temperature compensation mode, the CE controls
the GAIN_ADJ0, GAIN_ADJ1, and GAIN_ADJ2 registers
based on the temperature T found in the STEMP reg-
ister and on the coefficients describing the expected
behavior of VREF over temperature (in registers PPMC
and PPMC2, and available from the PPMCATE and
PPMC2ATE locations loaded from the OTP memory after
reset). The formula applied for the gain adjust settings is:
⋅⋅
=++
2
14 23
PPMC T PPMC2 T
GAIN_ADJ 16385
22
This operation mode compensates for the expected
variations of VREF over temperature. In this operation
mode, system factors still influence the meter’s accu-
racy over temperature. These factors include the current
sensors, their signal conditioning circuits, and the resis-
tive dividers for voltage. If these system factors can be
characterized, the resulting behavior of the system over
temperature can be compensated with new values for
PPM and PPMC2 that are a combination of the VREF
characteristics (as stored in PPMCATE and PPMCATE2)
and the sensor temperature characteristics. If a linear
and quadratic compensation is sufficient, the host can
load the new compensation values into the PPMC and
PPMC2 registers and have the CE code operate in inter-
nal temperature compensation mode.
Note: If the host does not set up PPMC and PPMC2, it
can void the accuracy of the MAX71020. The minimum
setup is to copy PPMCATE to PPMC and PPMC2ATE
to PPMC2. This sets up the standard digital tempera-
ture compensation for VREF.
If compensation with cubic and higher coefficients is
required, the calculation of the necessary GAIN_ADJ
values should be implemented in the host. In this case,
the host should set the EXT_TEMP bit in the CECONFIG
register to 1 and control the GAIN_ADJ registers directly.
It is possible to apply individual compensation schemes
for the voltage (GAIN_ADJ0) and current (GAIN_ADJ1,
GAINADJ2) channels.