Datasheet

MAX71020
Single-Chip Electricity Meter AFE
15Maxim Integrated
Note that the status byte indicates the status of the previ-
ous SPI transaction except for the status byte parity.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from
writing to arbitrary registers and possibly disturbing the
CE operation. For this reason, the SPI_SAFE mode was
created. In this mode, all SPI writes are disabled except
to the word containing the SPI_SAFE bit. This affords the
host one more layer of protection from inadvertent writes.
Functional Description
Theory of Operation
The energy delivered by a power source into a load can
be expressed as:
t
0
E V(t)I(t)dt=
∫
Assuming phase angles are constant, the following for-
mulae apply:
P = Real Energy [Wh] = V x A x cos φ x t
Q = Reactive Energy [VARh] = V x A x sin φ x t
S = Apparent Energy [VAh] =
22
PQ
+
For a practical meter, not only voltage and current ampli-
tudes, but also phase angles and harmonic content may
constantly change. Thus, simple RMS measurements are
inherently inaccurate. A modern solid-state electricity
meter IC such as the MAX71020 functions by emulating
the integral operation above, i.e., it processes current
and voltage samples through an ADC at a constant fre-
quency. As long as the ADC resolution is high enough
and the sample frequency is beyond the harmonic range
of interest, the current and voltage samples, multiplied
with the time period of sampling yield an accurate quan-
tity for the momentary energy. Summing the instanta-
neous energy quantities over time provides very accurate
results for accumulated energy.
Table 5. SPI Transaction (64 Bits)
Figure 3. SPI Slave Port—Typical READ and WRITE operations
24-BIT SETTING FIELD 8-BIT STATUS 32-BIT DATA
Address Dir Inv Address Inv Dir Status from Previous Transaction: status[7:0] Data
addr[10:0] RD addr_b[10:0] RD_b
Status
Parity
FIFO
OverRun
FIFO
UnderRun
Data
Parity
Setting
Mismatch
Reserved
Bad
CK Cnt
Bad
Address
data[31:0]
SERIAL READ
11-BIT ADDRESS
0
A10 A9 A1 A0
A10
RD
10 11 22 23 24 31 32 47 48 63
010112223243132474
86
3
D0D1D13D14D15D16D30D31ST0ST6ST7
X
11-BIT INVERTED
ADDRESS STATUS BYTEDATA [ADDR]RD
(FROM HOST) SPI_CSZ
(FROM HOST) SPI_CLK
(FROM HOST) SPI_DI
(FROM AM48) SPI_DO
(FROM AM48) SPI_DO
(FROM HOST) SPI_CSZ
(FROM HOST) SPI_CLK
(FROM HOST) SPI_DI
SERIAL WRITE
RD
11-BIT ADDRESS
11-BIT INVERTED
ADDRESS STATUS BYTEDATA [ADDR]RD RD
A9 A0 RD
A10 A9 A1 A0
HI-Z
HI-Z
A10
RD D31
ST7ST6 ST0
D30 D16 D15 D14 D13 D1 D0 XX
A9 A0 RD