Datasheet

MAX71020
Single-Chip Electricity Meter AFE
14Maxim Integrated
SPI Slave Port
The slave SPI port communicates directly with the host
controller and allows it to read and write the device
control registers. The interface to the slave port consists
of the SPI_CSZ, SPI_CLK, SPI_DI, and SPI_DO pins. The
host can also reset the MAX71020 through the SPI port by
writing a data pattern to the RESET register (see Table 7).
SPI Transactions
SPI transactions are configured to provide immunity to
electrical noise through redundancy in the command
segment and error checking in the data field. The
MAX71020 SPI transaction is exactly 64 bits; transactions
of any other length are rejected. Each SPI transaction has
the following fields (see Table 5):
●
A 24-bit setting packet, consisting of
11-bit address, MSB first
1-bit direction (1 means read)
11-bit inverted address, MSB first
1-bit inverted direction
●
An 8-bit status, consisting of the following bits
concerning the last transaction, starting from bit 7:
Parity of the status byte (0 or 1 could be correct)
FIFO overflow status bit (1 means error)
FIFO underrun status bit (1 means error)
Read or write data parity (0 or 1 could be correct)
(never both read and write; address is not included
in the parity)
Address or direction mismatch error bit
(1 means error) (1: error, 0 : no error)
A bit indicating whether or not the bit count was
exactly 64 (1 means error)
Out of bounds address, most likely due to SPI
safe bit or the memory manager (1 means error)
● A 32-bit packet of data, MSB first
If extra clocks are provided at the end during a read, all
zero is output and the status continues to be updated,
signaling an error. If extra clocks are provided at the
end during a write, the write is aborted and the status is
updated to signal an error.
●
None of the fields above are optional.
● If an error is detected during the address or direction
phase, no action is taken.
●
SPI_DO is high-Z while SPI_CSZ is high.
● SPI safe mode is supported, and SPI is not locked
out of this bit during SPI safe.
A typical SPI transaction is as follows. While SPI_CSZ
is high, the port is held in an initialized/reset state.
During this state, SPI_DO is held in high-Z state and all
transitions on SPI_CLK and SPI_DI are ignored. When
SPI_CSZ falls, the port begins the transaction on the first
rising edge of SPI_CLK. A transaction consists of the
fields shown in Table 5.
Table 4. Temperature Measurement Registers
NAME RST WK DIR DESCRIPTION
TEMP_PER[1:0] 0 — R/W
Sets the period between temperature measurements.
TEMP_PER TIME
0 Manual updates (see TEMP_START description)
1 Every accumulation cycle
2 Continuous
3 No updates
TEMP_START 0 — R/W
TEMP_PER[1:0] must be zero in order for TEMP_START to function. If TEMP_
PER[1:0] = 0, then setting TEMP_START starts a temperature measurement.
Hardware clears
TEMP_START when the temperature measurement is complete. The host
controller must wait for TEMP_START to clear before reading STEMP[10:0]
and before setting TEMP_START again.
STEMP[15:0] — — R The result of the temperature measurement.
VSENSE[7:0] — — R
The result of the temperature measurement (see the formula listed in the
Electrical Characteristics table).