Datasheet

Detailed Description
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. Whenever the μP is in an unknown state, it
should be held in reset. The MAX705–MAX708/MAX813L
assert reset during power-up and prevent code execution
errors during power-down or brownout conditions.
On power-up, once V
CC
reaches 1V, RESET is a
guaranteed logic low of 0.4V or less. As V
CC
rises, RESET
stays low. When V
CC
rises above the reset threshold, an
internal timer releases RESET after about 200ms. RESET
pulses low whenever V
CC
dips below the reset threshold,
i.e. brownout condition. If brownout occurs in the middle
of a previously initiated reset pulse, the pulse continues
for at least another 140ms. On power-down, once V
CC
falls below the reset threshold, RESET stays low and is
guaranteed to be 0.4V or less until V
CC
drops below 1V.
The MAX707/MAX708/MAX813L active-high RESET
output is simply the complement of the RESET output,
and is guaranteed to be valid with V
CC
down to 1.1V.
Some μPs, such as Intel’s 80C51, require an active-high
reset pulse.
Watchdog Timer
The MAX705/MAX706/MAX813L watchdog circuit
monitors the μP’s activity. If the μP does not toggle the
watchdog input (WDI) within 1.6sec and WDI is not three
stated, WDO goes low. As long as RESET is asserted or
the WDI input is three stated, the watchdog timer stays
cleared and will not count. As soon as reset is released
and WDI is driven high or low, the timer starts counting.
Pulses as short as 50ns can be detected.
Typically, WDO is not connected to the nonmaskable
interrupt input (NMI) of a μP. When V
CC
drops below
the reset threshold, WDO goes low whether or not
the watchdog timer has timed out yet. Normally this
would trigger an NMI interrupt, but RESET goes low
simultaneously, and thus overrides the NMI interrupt.
If WDI is left unconnected, WDO can be used as a low-
line output. Since oating WDI disables the internal timer,
WDO goes low only when V
CC
falls below the reset
threshold, thus functioning as a low-line output.
The MAX705/MAX706 have a watchdog timer and a
RESET output. The MAX707/MAX708 have both active-
high and active-low reset outputs. The MAX813L has both
an active-high reset output and a watchdog timer.
Manual Reset
The manual-reset input (MR) allows reset to be triggered
by a pushbutton switch. The switch is e󰀨ectively
debounced by the 140ms minimum reset pulse width. MR
is TTL/CMOS-logic compatible, so it can be driven by an
external logic line. MR can be used to force a watchdog
timeout to generate a reset pulse in the MAX705/ MAX706/
MAX813L. Simply connect WDO to MR.
Figure 1. MAX705/MAX706/MAX813L Block Diagram Figure 2. MAX707/MAX708 Block Diagram
WATCHDOG
TIMER
TIMEBASE FOR
RESET AND
WATCHDOG
RESET
GENERATOR
V
CC
250µA
8
WDO
7
RESET
(RESET)
5
PFO
GND3
1.25V
4.65V*
* 4.40V FOR MAX7O6.
( ) ARE FOR MAX813L ONLY.
6
WDI
1
MR
2
V
CC
4
PFI
MAX705
MAX706
MAX813L
WATCHDOG
TRANSITION
DETECTOR
RESET
GENERATOR
8
RESET
7
RESET
5
PFO
1.25V
4.65V*
* 4.40V FOR MAX7O6.
1
MR
2
V
CC
4
PFI
MAX707
MAX708
V
CC
250µA
GND3
MAX705–MAX708/MAX813L MAX705–MAX708/MAX813L
Low-Cost, μP Supervisory Circuits
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