Datasheet

24 Maxim Integrated
280MHz to 450MHz Programmable
ASK/FSK Transmitter
MAX7060
The 4 MSBs of FHigh0, fhi[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0])
are the fractional part of the divider.
Table 14. FSK High-Frequency 1 (FHigh1) Register (Address: 0x0A)
Table 15. ASK Center-Frequency 0 (FCenter0) Register (Address: 0x0B)
Table 16. ASK Center-Frequency 1 (FCenter1) Register (Address: 0x0C)
Table 17. FSK Low-Frequency 0 (FLow0) Register (Address:0x0D)
Table 18. FSK Low-Frequency 1 (FLow1) Register (Address: 0x0E)
Table 19. Maximum and Minimum Values for Frequency Divider
Table 20. Frequency-Load (FLoad) Register (Address: 0x0F)
The 4 MSBs of FCenter0, fce[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fce[11:0)
are the fractional part of the divider.
When fce[11:0] are all zeros and ASK mode is selected (mode bit = 0), the PLL works in the fixed-N mode, which
reduces current consumption and reference spurs. Set pllbw bit high (Conf0 register, bit 5). For all other combinations,
the PLL works in fractional-N mode.
The 4 MSBs of FLow0, flo[15:12], are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0])
are the fractional part of the divider.
BIT NAME FUNCTION
7:0 fhi[7:0] 8-bit lower byte of high-frequency divider for FSK
BIT NAME FUNCTION
7:0 fce[15:8] 8-bit upper byte of frequency divider for ASK
BIT NAME FUNCTION
7:0 fce[7:0] 8-bit lower byte of frequency divider for ASK
BIT NAME FUNCTION
7:0 flo[15:8] 8-bit upper byte of low-frequency divider for FSK
BIT NAME FUNCTION
7:0 flo[7:0] 8-bit lower byte of low-frequency divider for FSK
DECIMAL VALUE fhi[15:0], fce[15:0], flo[15:0]
12.0220 0xC05A
2.9536 0x2F42
BIT NAME FUNCTION
0 hop
Effectively changes the PLL frequency to the ones written in registers 0x09 to 0x0E. This is a self-reset bit
and is reset to zero after the operation is completed.