Datasheet

23Maxim Integrated

280MHz to 450MHz Programmable

ASK/FSK Transmitter

MAX7060

where:

— Reserved signals

nock No-clock flag (1) if crystal oscillator is disabled, and (0) if clock activity is observed

ckout Clock output signal, according to programmed dividers (ckdiv[2:0])

lockdet PLL lock-detect flag

Table 9. IO Configuration 1 (IOConf1) Register (Address: 0x05)

Table 10. ASK Digital Shaping Time Step (Tstep) Register (Address: 0x06)

Table 11. PA Digital Shaping Amplitude Step (PAstep) Register (Address: 0x07)

Table 12. PA Power (PApwr) Register (Address: 0x08)

Table 13. FSK High-Frequency 0 (FHigh0) Register (Address: 0x09)

BIT NAME FUNCTION

6:4 gp2s[2:0]

GPO2 output selection

CS_DEV Bit 2 Bit 1 Bit 0 GPO2_MOD

0 X X X SPI Data Output

1 0 0 0 lockdet

1 0 0 1 —

1 0 1 0 ckout

1 0 1 1 —

1 1 0 0 —

1 1 0 1 nock

1 1 1 0 —

1 1 1 1 —

2:0 gp1s[2:0]

GPO1 output selection

Bit 2 Bit 1 Bit 0 GPO1

0 0 0 lockdet

0 0 1 —

0 1 0 ckout

0 1 1 —

1 0 0 —

1 0 1 nock

1 1 0 —

1 1 1 —

BIT NAME FUNCTION

3:0 tstep[3:0] Time interval value used in digital shaping, in increments of 4/f

XTAL

BIT NAME FUNCTION

4:0 pastp[4:0] Power step in digital shaping, in increments of 1dB

BIT NAME FUNCTION

4:0 papwr[4:0] Final PA output power setting

BIT NAME FUNCTION

7:0 fhi[15:8] 8-bit upper byte of high-frequency divider for FSK