Datasheet

21Maxim Integrated
280MHz to 450MHz Programmable
ASK/FSK Transmitter
MAX7060
Table 2. Configuration Registers (continued)
Table 3. Identification (Ident) Register (Address: 0x00)
Table 4. Configuration 0 (Conf0) Register (Address: 0x01)
Table 5. Configuration 1 (Conf1) Register
(Address: 0x02)
Table 6. Crystal Divide Settings for Clock
Output
REGISTER ADDRESS
DATA
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE
FLow0 0x0D flo_15 flo_14 flo_13 flo_12 flo_11 flo_10 flo_9 flo_8 R/W
FLow1 0x0E flo_7 flo_6 flo_5 flo_4 flo_3 flo_2 flo_1 flo_0 R/W
FLoad 0x0F — — — — — — — hop R/W
EnableReg 0x10 — — — — — — — enable R/W
DataReg 0x11 — — — — — — — datain R/W
Status 0x12 status_7 status_6 status_5 status_4 status_3 status_2 status_1 status_0 R
BIT NAME FUNCTION
7:0 ident Read-only register used for identification purpose. The content of this register is always 0xA6.
BIT NAME FUNCTION
6 gp1bst
0 = Normal GPO1 output driver
1 = Extended driving capability on GPO1
5 pllbw
PLL bandwidth setting, low (0) = 300kHz or high (1) = 600kHz; 300kHz is recommended for fractional-N
and 600kHz for fixed-N (ASK mode only)
4:3 anshp[1:0]
Control time constants of the analog shaping (bias inductor connected to the ROUT pin)
anshp[1:0] Rise/fall time
00 ROUT open-circuited, 4Fs pulse extension present
01 nominal 3.0Fs rise/fall time
10 nominal 1.5Fs rise/fall time
11 no analog shaping, no 4Fs pulse extension
2 clksby Crystal clock output enable (1) while part is in standby mode
1 clkout Crystal clock output enable (1) on GPO1 output, gp1s[2:0] = 0x2
0 mode ASK (0) or FSK (1)
BIT NAME FUNCTION
7:5 ckdiv[2:0] 3-bit clock output frequency divider
4:0 cap[4:0] 5-bit capacitor setting
ckdiv[2:0]
CRYSTAL FREQUENCY
DIVIDED BY
000 1
001 2
010 4
011 8
1XX 16