Datasheet

20 Maxim Integrated

280MHz to 450MHz Programmable

ASK/FSK Transmitter

MAX7060

The following tables provide information on the MAX7060 registers.

Table 1. Register Summary

Table 2. Configuration Registers

Ident 0x00 Read-only register used for identification purpose. The content of this register is always 0xA6.

Conf0 0x01

Configuration 0 register. Controls the GPO1 boost mode, PLL bandwidth, analog shaping, crys-

tal clock output, and the modulation mode (ASK/FSK).

Conf1 0x02

Configuration 1 register. Controls the clock output frequency divider and the capacitance at the

PA output.

Conf2 0x03 Configuration 2 register. Controls the emulation mode.

IOConf0 0x04 IO configuration 0 register. Selects the status register bus for SPI operation.

IOConf1 0x05 IO configuration 1 register. Selects the outputs of GPO1 and GPO2_MOD pins.

Tstep 0x06 Digital shaping time step register. Controls the time step in the digital shaping.

PAstep 0x07 Digital shaping power step register. Controls the power step in the digital shaping.

PApwr 0x08 Final power register. Controls the final output power.

FHigh0 0x09 High-frequency 0 register (upper byte). Sets the high frequency in FSK transmission.

FHigh1 0x0A High-frequency 1 register (lower byte). Sets the high frequency in FSK transmission.

FCenter0 0x0B Center-frequency 0 register (upper byte). Sets the carrier frequency in ASK transmission.

FCenter1 0x0C Center-frequency 1 register (lower byte). Sets the carrier frequency in ASK transmission.

FLow0 0x0D Low-frequency 0 register (upper byte). Sets the low frequency in FSK transmission.

FLow1 0x0E Low-frequency 1 register (lower byte). Sets the low frequency in FSK transmission.

FLoad 0x0F Frequency-load register. Performs the frequency-load function.

EnableReg 0x10 Enable register. Register equivalent of ENABLE pin.

DataReg 0x11 Datain register. Register equivalent of DIN pin.

Status 0x12 Status register

DATA

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE

Ident 0x00 1 0 1 0 0 1 1 0 R

Conf0 0x01 — gp1bst pllbw anshp_1 anshp_0 clksby clkout mode R/W

Conf1 0x02 ckdiv_2 ckdiv_1 ckdiv_0 cap_4 cap_3 cap_2 cap_1 cap_0 R/W

Conf2 0x03 fixed fxmode fxpwr_1 fxpwr_0 fxhdev fxfrq_2 fxfrq_1 fxfrq_0 R/W

IOConf0 0x04 — — — — — tmux_2 tmux_1 tmux_0 R/W

IOConf1 0x05 — gp2s_2 gp2s_1 gp2s_0 — gp1s_2 gp1s_1 gp1s_0 R/W

Tstep 0x06 — — — — tstep_3 tstep_2 tstep_1 tstep_0 R/W

PAstep 0x07 — — — pastp_4 pastp_3 pastp_2 pastp_1 pastp_0 R/W

PApwr 0x08 — — — papwr_4 papwr_3 papwr_2 papwr_1 papwr_0 R/W

FHigh0 0x09 fhi_15 fhi_14 fhi_13 fhi_12 fhi_11 fhi_10 fhi_9 fhi_8 R/W

FHigh1 0x0A fhi_7 fhi_6 fhi_5 fhi_4 fhi_3 fhi_2 fhi_1 fhi_0 R/W

FCenter0

0x0B fce_15 fce_14 fce_13 fce_12 fce_11 fce_10 fce_9 fce_8 R/W

FCenter1 0x0C fce_7 fce_6 fce_5 fce_4 fce_3 fce_2 fce_1 fce_0 R/W