Datasheet

17Maxim Integrated
280MHz to 450MHz Programmable
ASK/FSK Transmitter
MAX7060
Read All: Within two CS_DEV cycles, the read-all command is implemented as follows:
CS_DEV Cycle 1 CS_DEV Cycle 2
SDI_PWR1: <0x03> <Address N> <0x00> <0x00> <0x00> ... <0x00>
GPO2_MOD: <Data N><Data N + 1><Data N + 2>...<Data N + n>
Reset: An SPI reset command is implemented as follows:
SDI_PWR1: <0x04>
An internal active-low master reset pulse is generated, from the falling edge of the last SCLK_PWR0 signal to the falling
edge of the following CS_DEV signal (t
HCS
+ t
CSH
).
Figure 5. SPI Read-All Command Format
Figure 6. SPI Reset Command Format
Figure 4. SPI Read Command Format
A7
SCLK_PWR0
SDI_PWR1
GPO2_MOD
CS_DEV
READ COMMAND (0x02) ADDRESS 1 ADDRESS 2
ADDRESS N 0x00
A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D0D7
DATA 1 DATA 2 DATA N
A7
SCLK_PWR0
GPO2_MOD
SDI_PWR1
CS_DEV
READ-ALL COMMAND (0x03) ADDRESS N
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D0D7
DATA N
DATA N + 1
A6 A5 A4 A3 A2 A1 A0
DATA N + n
SCLK_PWRO
CS_DEV
INTERNAL
RESET PULSE
RESET COMMAND (0x04)
SDI_PWR1