Datasheet

15Maxim Integrated
280MHz to 450MHz Programmable
ASK/FSK Transmitter
MAX7060
Crystal (XTAL) Oscillator
The XTAL oscillator in the MAX7060 is designed to pres-
ent a capacitance of approximately 6pF between the
XTAL1 and XTAL2 pins. In most cases, this corresponds
to a 8pF load capacitance applied to the external crystal
when typical PCB parasitics are added. It is very impor-
tant to use a crystal with a load capacitance equal to the
capacitance of the MAX7060 crystal oscillator plus PCB
parasitics. If a crystal designed to oscillate with a differ-
ent load capacitance is used, the crystal is pulled away
from its stated operating frequency, introducing an error
in the reference frequency. A crystal designed to oper-
ate at a higher load capacitance than the value specified
for the oscillator is always pulled higher in frequency.
Adding capacitance to increase the load capacitance
on the crystal increases the startup time and can prevent
oscillation altogether.
In actuality, the oscillator pulls every crystal. The crystal’s
natural frequency is really below its specified frequency,
but when loaded with the specified load capacitance,
the crystal is pulled and oscillates at its specified fre-
quency. This pulling is already accounted for in the
specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency pull-
ing is given by:
6
M
P
CASE LOAD CASE SPEC
C
11
f 10
2CC CC

= −×

++

where:
f
P
is the amount the crystal frequency pulled in ppm
C
M
is the motional capacitance of the crystal
C
CASE
is the case capacitance
C
SPEC
is the specified load capacitance
C
LOAD
is the actual load capacitance
When the crystal is loaded as specified (i.e., C
LOAD
=
C
SPEC
), the frequency pulling equals zero.
General-Purpose Output
(GPO)/Clock Outputs
The MAX7060 has two GPO pins in SPI mode (GPO2_
MOD and GPO1) and one GPO in manual mode (GPO1).
The GPO1 pin can serve as a clock for a microprocessor
or any other GPO function in SPI mode. In manual mode,
this pin outputs the synthesizer lock-detect (lockdet)
status, after which the user can send data through the
DIN pin.
The GPO2_MOD pin acts as the SPI data output when
the CS_DEV pin is low, in SPI mode. When CS_DEV is
high, it acts as a GPO that can output various internal
signals, such as the synthesizer lock detect (lockdet).
In SPI mode, the output clock that can be routed through
GPO1 is a divided version of the crystal frequency. The
divide ratio is set through the MAX7060 registers, and
the divide settings are 1 (no division), 2, 4, 8, or 16.
When driving an output clock through GPO1, the gp1bst
bit (register Conf0, address 0x01, bit 6) can be set to
1 to increase GPO1 drive strength. If even more drive
capability is required, the user should provide an exter-
nal buffer.
Serial Peripheral Interface (SPI)
The MAX7060 utilizes a 4-wire SPI protocol for pro-
gramming its registers, configuring and controlling the
operation of the whole transmitter. For SPI operation, the
FREQ2, FREQ1, and FREQ0 pins must be reset to 0.
The following digital I/Os control the operation of the SPI:
CS_DEV Active-low SPI chip select
SDI_PWR1 SPI data Input
SCLK_PWR0 SPI clock
GPO2_MOD SPI data output
Figure 2 shows the general timing diagram of the SPI
protocol.
Any number of 8-bit data bursts (Data 1, Data 2 … Data
n) can be sent within one cycle of the CS_DEV pin, to
allow for burst-write or burst-read operations. The SPI
data output signal is routed through the GPO2_MOD pin
when CS_DEV is low.