Datasheet

Ensuring a Valid RESET Output
Down to V
CC
= 0V
When V
CC
falls below 1V, the MAX703/MAX704 RESET
output no longer sinks current; it becomes an open circuit.
High-impedance CMOS logic inputs can drift to unde-
termined voltages if left as open circuits. If a pulldown
resistor is added to the RESET pin as shown in Figure 6,
any stray charge or leakage currents will flow to ground,
holding RESET low. Resistor value R1 is not critical. It
should be about 100kΩ, which is large enough not to load
RESET and small enough to pull RESET to ground.
Replacing the Backup Battery
The backup battery can be removed while V
CC
remains
valid without triggering a reset. As long as V
CC
stays
above the reset threshold, battery-backup mode cannot
be entered. This is an improvement on switchover ICs
that initiate a reset when V
CC
and V
BATT
are at or near
the same voltage level (regardless of the reset threshold
voltage). If the voltage on the unconnected V
BATT
pin
floats up toward V
CC
, this condition alone cannot initiate
a reset when using the MAX703/MAX704.
Adding Hysteresis to the
Power-Fail Comparator
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of PFO when
V
IN
is near the power-fail comparator trip point. Figure 7
shows how to add hysteresis to the power-fail compara-
tor. Select the ratio of R1 and R2 so that PFI sees 1.25V
when V
IN
falls to the desired trip point (V
TRIP
). Resistor
R3 adds hysteresis. It will typically be an order of magni-
tude greater than R1 or R2. The current through R1 and
R2 should be at least 1μA to ensure that the 25nA (max)
PFI input current does not shift the trip point. R3 should
be larger than 10kΩ to prevent it from loading down the
PFO pin. Capacitor C1 adds additional noise rejection.
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 8’s circuit. When
the negative supply is valid, PFO is low. When the nega-
tive supply voltage droops, PFO goes high. This circuit’s
accuracy is affected by the PFI threshold tolerance, the
V
CC
voltage, and resistors R1 and R2.
Figure 6. RESET Valid to Ground Circuit
Figure 7. Adding Hysteresis to the Power-Fail Comparator
Figure 8. Monitoring a Negative Voltage
V
CC
V
OUT
V
BATT
RESET
R1
MAX703
MAX704
V
IN
TOP
+5V
+5V
0V
0V V
L
V
TRIP
V
IN
R1
R2
R3
PFI
*OPTIONAL
C1*
V
CC
GND
PFO
PFO
V
H
MAX703
MAX704
12
TRIP
2
23
H
1 23
RR
V 1.25
R
R ||R
V 1.25 /
R R ||R

+
=



=

+

L
1 32
V 1.25
5 1.25 1.25
R RR
−
−
+=
V-
+5V
+5V
0V
0V
V
TRIP
V-
R1
R2
PFI
NOTE: V
TRIP
IS NEGATIVE
V
CC
GND
PFO
PFO
MAX703
MAX704
TRIP
12
1.25 V
5 1.25
RR
−
−
=
MAX703/MAX704 Low-Cost Microprocessor Supervisory
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