Datasheet

PIN
NAME FUNCTION
TSSOP TQFN
1 29 XTAL1 Crystal Input 1 (see the Phase-Locked Loop section)
2, 7 4, 30 AVDD
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator, and should be bypassed to AGND with a 0.1µF capacitor as close
as possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and
bypassed to AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage
Regulator section and the Typical Application Circuit).
3 31 LNAIN Low-Noise Amplier Input (see the Low-Noise Amplier section)
4 32 LNASRC
Low-Noise Amplier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (see the Low-Noise Amplier section).
5, 10 2, 7 AGND Analog Ground
6 3 LNAOUT
Low-Noise Amplier Output. Connect to mixer input through an LC tank lter (see the Low-
Noise Amplier section).
8 5 MIXIN1 1st Differential Mixer Input. Connect to LC tank lter from LNAOUT.
9 6 MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to V
DD3
side of the LC tank.
11 8 IRSEL
Image-Rejection Select. Set V
IRSEL
= 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V
IRSEL
= V
DD5
to center image
rejection at 433MHz.
12 9 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass lter.
13 10 DGND Digital Ground
14 11 DVDD
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a
0.01µF capacitor as close as possible to the pin (see the Typical Application Circuit).
15 12 AC Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor.
16 14 XTALSEL
Crystal Divider Ratio Select. Drive XTALSEL low to select f
LO
/f
XTAL
ratio of 64, or drive
XTALSEL high to select f
LO
/f
XTAL
ratio of 32.
17 15 IFIN1
1st Differential Intermediate-Frequency Limiter Amplier Input. Bypass to AGND with a
1500pF capacitor as close to the pin as possible.
18 16 IFIN2
2nd Differential Intermediate-Frequency Limiter Amplier Input. Connect to the output of a
10.7MHz bandpass lter.
19 17 DFO Data Filter Output
20 18 DSN Negative Data Slicer Input
21 19 OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22 20 DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data lter.
23 22 DSP Positive Data Slicer Input
24 23 V
DD5
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the
pin. For +5V operation, V
DD5
is the input to an on-chip voltage regulator whose +3.2V output
appears at the pin 2 AVDD pin (see the Voltage Regulator section and the Typical Application
Circuit).
25 24 DATAOUT Digital Baseband Data Output
26 26 PDOUT Peak-Detector Output
27 27 SHDN
Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with
a 100kΩ resistor.
MAX7033 315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
www.maximintegrated.com
Maxim Integrated │ 8
Pin Description