Datasheet

PIN
NAME FUNCTION
MAX696 MAX697
1 — V
BATT
Backup-Battery Input. Connect to ground if a backup battery is not used.
2 — V
OUT
The higher of V
CC
or V
BATT
is internally switched to V
OUT
. Connect V
OUT
to V
CC
if
V
OUT
and V
BATT
are not used.
3 3 V
CC
+5V Input
4 5 GND 0V Ground Reference for All Signals
5 — BATT ON
BATT ON goes High when V
OUT
is Internally Switched to the V
BATT
Input. It goes
low when V
OUT
is internally switched to V
CC
. The output typically sinks 7mA and
can directly drive the base of an external pnp transistor to increase the output current
above the 50mA rating of V
OUT
.
6 6 LOW LINE
LOW LINE goes Low when LL
IN
Falls Below 1.3V. It returns high as soon as LL
IN
rises above 1.3V. See Figure 5.
7 7 OSC IN
OSC IN Sets the Reset Delay Timing and Watchdog Timeout Period when OSC SEL
Floats or is Driven Low. The timing can also be adjusted by connecting an external
capacitor to this pin. See Figure 7. When OSC SEL is high, OSC IN selects between
fast and slow watchdog timeout periods
8 8 OSC SEL
When OSC SEL is Unconnected or Driven High, the Internal Oscillator Sets the
Reset Time Delay and Watchdog Timeout Period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See
Table 1.
9 9 PFI
PFI is the Noninverting Input to the Power-Fail Comparator. When PFI is less than
1.3V, PFO goes low. Connect PFI to GND or V
OUT
when not used. See Figure 1.
10 10 PFO
PFO is the Output of the Power-Fail Comparator. It goes low when PFI is less than
1.3V. The comparator is turned off and PFO goes low when V
CC
is below V
BATT
.
11 11 WDI
The Watchdog Input, WDI, is a Three-Level Input. If WDI remains either high or low
for longer than the watchdog timeout period, RESET pulses low and WDO goes low.
The watchdog timer is disabled when WDI is left oating or is driven to mid-supply.
The timer resets with each transition at the watchdog timer input.
12 2 N.C. No Connection. Leave this pin open.
13 4 LL
IN
Low-Line Input. LL
IN
is the CMOS input to a comparator whose other input is a
precision 1.3V reference. The output is LOW LINE and is also connected to the reset
pulse generator. See Figure 2.
14 14 WDO
The Watchdog Output, WDO, goes Low if WDI Remains either High or Low for
Longer than the Watchdog Timeout Period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes
high when LOW LINE goes low.
15 15 RESET
RESET goes Low whenever LL
IN
Falls Below 1.3V or V
CC
Falls Below the V
BATT
Input Voltage. RESET remains low for 50ms after LL
IN
goes above 1.3V. RESET also
goes low for 50ms if the watchdog timer is enabled but not serviced within its timeout
period. The RESET pulse width can be adjusted as shown in Table 1.
16 16 RESET RESET is an Active-High Output. It is the inverse of RESET.
MAX696/MAX697 Microprocessor Supervisory Circuits
www.maximintegrated.com
Maxim Integrated │ 5
Pin Description