Datasheet

Applications Information
Adding Hysteresis to the
Power-Fail Comparator
Since the power-fail comparator circuit is noninvert-
ing, hysteresis can be added by connecting a resistor
between the PFO output and the PFI input as shown in
Figure 7. When PFO is low, resistor R3 sinks current from
the summing junction at the PFI pin. When PFO is high,
the series combination of R3 and R4 source current into
the PFI summing junction.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled
under program control by driving WDI with a three-state
buffer (Figure 8). The drawback to this circuit is that a
software fault may erroneously three-state the buffer,
thereby preventing the MAX696/MAX697 from detecting
that the microprocessor is no longer working. In most
cases, a better method is to extend the watchdog period
rather than disabling the watchdog. See Figure 9. When
the control input is high, the OSC SEL pin is low and
the watchdog timeout is set by the external capacitor.
A 0.01μF capacitor sets a watchdog timeout delay of
100s. When the control input is low, the OSC SEL pin is
driven high, selecting the internal oscillator. The 100ms or
the 1.6s period is chosen, depending on which diode in
Figure 9 is used.
Figure 7. Adding Hysteresis to the Power-Fail Voltage
Comparator
Figure 8. Disabling the Watchdog Under Program Control
Figure 9. Selecting Internal or External Watchdog Timeout
V
CC
PFO
PFI
GND
7805
7V - 15V
+5V
R1
75kΩ
R4
10kΩ
R2
13kΩ
R3
300kΩ
TOP
V
H
= 9.125V
V
L
= 7.9V
HYSTERESIS = 1.23V
V
H
= 1.3V
V
L
= 1.3V
{ }
1 + +
R1
R2
R1
R3
{ }
1 + +
R1
R2
(5V - 1.3V) R1
1.3V (R3 + R4)
HYSTERESIS 5V x
R1
R3
ASSUMING R4 <<
R3
MAX696
MAX697
WDI
GND
+5V
WATCHDOG
STROBE
WATCHDOG
DISABLE
EN
V
CC
MAX696
MAX697
OSC SEL
OSC IN
GND
+5V
V
CC
LOW = INTERNAL
WATCHDOG TIMEOUT
HI = EXTERNAL
WATCHDOG
TIMEOUT
CONNECT FOR
100ms TIMEOUT
WHEN INTERNAL
TIMEOUT IS
SELECTED
CONNECT FOR
1.6s INTERNAL
TIMEOUT
MAX696
MAX697
MAX696/MAX697 Microprocessor Supervisory Circuits
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