Datasheet

10-Port Constant-Current LED Drivers and I/O
Expanders with PWM Intensity Control
The MAX6966/MAX6967 are written to using the follow-
ing sequence (Figure 11):
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift reg-
ister.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low).
5) Take SCLK low (if not already low).
If fewer or greater than 16 bits are clocked into the
MAX6966/MAX6967 between taking CS low and taking
CS high again, the MAX6966/MAX6967 store the last 16
bits received, including the previous transmission(s).
The general case is when n bits (where n > 16) are
transmitted to the MAX6966/MAX6967. The last bits
comprising bits {n-15} to {n}, are retained, and are par-
allel loaded into the 16-bit latch as bits D15 to D0,
respectively (Figure 12).
Reading Device Registers
Any register data within the MAX6966/MAX6967 can be
read by sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last.
D15 is high, indicating a read command and bits
D14 through D8 contain the address of the register
to read. Bits D7 to D0 contain dummy data, which is
discarded.
4) Take CS high (either while SCLK is still high after
clocking in the last data bit, or after taking SCLK
low). Positions D7 through D0 in the shift register are
now loaded with the register data addressed by bits
D15 through D8.
5) Take SCLK low (if not already low).
6) Issue another read or write command, and examine
the bit stream at DOUT; the second 8 bits are the
contents of the register addressed by bits D14
through D8 in step 3).
.
D15
= 0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 = 0
CS
SCLK
DIN
DOUT
Figure 11. 16-Bit Write Transmission to the MAX6966/MAX6967
.
N-15
N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16
BIT
1
BIT
2
N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N
CS
SCLK
DIN
DOUT
Figure 12. Transmission of More than 16 Bits to the MAX6966/MAX6967
MAX6966/MAX6967
Maxim Integrated
23