Datasheet

MAX6956
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX6956, the
MAX6956 generates the acknowledge bit because the
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port LED Display Driver and I/O Expander
8 _______________________________________________________________________________________
Figure 2. 2-Wire Serial Interface Timing Details
SCL
SDA
START CONDITIONSTOP CONDITION
REPEATED START CONDITION
START CONDITION
t
SU, DAT
t
HD, DAT
t
LOW
t
HD, STA
t
HIGH
t
R
t
F
t
SU, STA
t
HD, STA
t
SU, STO
t
BUF
Figure 3. Standard Stop Conditions
SDA
SCL
S
START
CONDITION
P
STOP
CONDITION
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer