Datasheet

MAX6956
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port LED Display Driver and I/O Expander
_______________________________________________________________________________________ 3
Note 1: All parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 5: I
SINK
≤ 6mA. C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
ELECTRICAL CHARACTERISTICS (continued)
( Typical Operating Circuit , V+ = 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V+ = 2.5V, V
LED
= 2.3V at maximum LED
current
9.5 13.5 18
V+ = 3.3V, V
LED
= 2.4V at maximum LED
current (Note 2)
18.5 24 27.5
Port Drive LED Sink Current,
Port Configured as LED Driver
I
DIGIT
V+ = 5.5V, V
LED
= 2.4V at maximum LED
current
19 25 30
mA
V+ = 2.5V, V
OUT
= 0.6V at maximum sink
current
18.5 23 28
Port Drive Logic Sink Current,
Port Configured as LED Driver
I
DIGIT_SC
V+ = 5.5V, V
OUT
= 0.6V at maximum sink
current
19 24 28
mA
Input High-Voltage SDA, SCL,
AD0, AD1
V
IH
0.7
✕
V+
V
Input Low-Voltage SDA, SCL,
AD0, AD1
V
IL
0.3
✕
V+
V
Input Leakage Current SDA, SCL I
IH
, I
IL
-50 50 nA
Input Capacitance (Note 2) 10 pF
Output Low-Voltage SDA V
OL
I
SINK
= 6mA 0.4 V
TIMING CHARACTERISTICS (Figure 2)
(V+ = 2.5V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Serial Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3 µs
Hold Time (Repeated) START
Condition
t
HD
,
STA
0.6 µs
Repeated START Condition
Setup Time
t
SU
,
STA
0.6 µs
STOP Condition Setup Time t
SU
,
STO
0.6 µs
Data Hold Time t
HD
,
DAT
(Note 3) 15 900 ns
Data Setup Time t
SU
,
DAT
100 ns
SCL Clock Low Period t
LOW
1.3 µs
SCL Clock High Period t
HIGH
0.7 µs
Rise Time of Both SDA and SCL
Signals, Receiving
t
R
(Notes 2, 4)
20 +
0.1C
b
300 ns
Fall Time of Both SDA and SCL
Signals, Receiving
t
F
(Notes 2, 4)
20 +
0.1C
b
300 ns
Fall Time of SDA Transmitting t
F,TX
(Notes 2, 5)
20 +
0.1C
b
250 ns
Pulse Width of Spike Suppressed t
SP
(Notes 2, 6) 0 50 ns
Capacitive Load for Each Bus
Line
C
b
(Note 2) 400 pF