Datasheet

MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = +3.0V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Slow Segment Blink Period
(Internal Oscillator)
f
S LOWBLIN K
Eight digits scanned, OSC = RC oscillator,
R
SET
= 56kΩ, C
SET
= 27pF
1s
Fast Segment Blink Period
(Internal Oscillator)
f
FASTBLIN K
Eight digits scanned, OSC = RC oscillator,
R
SET
= 56kΩ, C
SET
= 27pF
0.5 s
Fast or Slow Segment Blink Duty
Cycle (Note 2)
49.9 50 50.1 %
Digit Drive Sink Current I
DIGIT
T
A
= +25°C, V
LED
= 2.4V 240 320 400 mA
Segment Drive Source Current I
SEG
T
A
= +25°C, V
LED
= 2.4V -30 -40 -50 mA
Digit Drive Sink Current (Note 2) I
DIGIT
T
A
= +25°C, V+ = 2.7V to 3V, V
LED
= 2.2V 80 mA
Segment Drive Source Current
(Note 2)
I
SEG
T
A
= +25°C, V+ = 2.7V to 3V, V
LED
= 2.2V -10 mA
Slew Rate Rise Time ∆I
SEG
/∆tT
A
= +25°C 35 mA/µs
LOGIC INPUTS
Input Current DIN, CLK, CS I
IH
, I
IL
V
IN
= 0 or V+ -2 2 µA
Logic High Input Voltage DIN,
CLK, CS
V
IH
2.4 V
Logic Low Input Voltage DIN,
CLK, CS
V
IL
0.4 V
H yster esi s V ol tag e D IN , C LK, C S ∆V
I
0.5 V
TIMING CHARACTERISTICS (Figure 1)
CLK Clock Period t
CP
38.4 ns
CLK Pulse Width High t
CH
19 ns
CLK Pulse Width Low t
CL
19 ns
C S Fall to CLK Ri se S etup Ti m et
CSS
9.5 ns
CLK Ri se to CS Rise Hold Time t
CSH
3ns
DIN Setup Time t
DS
9.5 ns
DIN Hold Time t
DH
0ns
CS Pulse High t
CSW
19 ns
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)
CLK Clock Period t
CP
50 ns
CLK Pulse Width High t
CH
24 ns
CLK Pulse Width Low t
CL
24 ns
C S Fall to CLK Ri se Setup Time t
CSS
12 ns
CLK Ri se to CS Rise Hold Time t
CSH
4ns
DIN Setup Time t
DS
12 ns
DIN Hold Time t
DH
4ns
CS Pulse High t
CSW
24 ns
Note 1: All parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.