Datasheet

MAX691A/MAX693A/MAX800L/MAX800M
Microprocessor Supervisory Circuits
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Chip-Enable Signal Gating
The MAX691A/MAX693A/MAX800L/MAX800M provide
internal gating of chip-enable (CE) signals to prevent
erroneous data from being written to CMOS RAM in the
event of a power failure. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled, prevent-
ing erroneous data from corrupting the CMOS RAM. All
these parts use a series transmission gate from
–
CE IN to
CE OUT (Figure 4).
The 10ns max CE propagation delay from CE IN to CE
OUT enables the parts to be used with most µPs.
Chip-Enable Input
The Chip-Enable Input (CE IN) is high impedance (dis-
abled mode) while RESET and RESET are asserted.
During a power-down sequence where V
CC
falls below
the reset threshold or a watchdog fault,
–
CE IN assumes
a high-impedance state when the voltage at CE IN
goes high or 15µs after reset is asserted, whichever
occurs first (Figure 5).
During a power-up sequence, CE IN remains high
impedance, regardless of CE IN activity, until reset is
deasserted following the reset timeout period.
In the high-impedance mode, the leakage currents into
this terminal are ±1µA max over temperature. In the
low-impedance mode, the impedance of
–
CE IN appears
as a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to
–
CE IN and the capacitive loading on the Chip-
Enable Output (
–
CE OUT) (see Chip-Enable Propagation
Delay vs. CE OUT Load Capacitance in the Typical
Operating Characteristics). The CE propagation delay
is production tested from the 50% point of
–
CE IN to the
50% point of
–
CE OUT using a 50Ω driver and 50pF of
load capacitance (Figure 6). For minimum propagation
delay, minimize the capacitive load at CE OUT, and
use a low output-impedance driver.
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is
equivalent to 75Ω in series with the source driving CE
IN. In the disabled mode, the 75Ω transmission gate is
off and CE OUT is actively pulled to V
OUT
. This source
turns off when the transmission gate is enabled.
–
L
—
O
—
W
——
L
—
I
—
N
—
E
–
Output
LOW LINE is the buffered output of the reset threshold
comparator. LOW LINE typically sinks 3.2mA at 0.1V.
For normal operation (V
CC
above the LOW LINE thresh-
old), LOW LINE is pulled to V
OUT
.
Power-Fail Comparator
The power-fail comparator is an uncommitted comparator
that has no effect on the other functions of the IC.
Common uses include low-battery indication (Figure 7),
and early power-fail warning (see Typical Operating
Circuit).
Power-Fail Input
Power Fail Input (PFI) is the input to the power-fail com-
parator. It has a guaranteed input leakage of ±25nA
max over temperature. The typical comparator delay is
25µs from V
IL
to V
OL
(power failing), and 60µs from V
IH
to V
OH
(power being restored). If PFI is not used, con-
nect it to ground.
OSC SEL
OSC IN
7
8
EXTERNAL
OSCILLATOR
OSC SEL
OSC IN
7
8
EXTERNAL
CLOCK
OSC SEL
OSC IN
7
8
INTERNAL OSCILLATOR
100ms WATCHDOG
OSC SEL
OSC IN
7
8
INTERNAL OSCILLATOR
1.6sec WATCHDOG
MAX691A
MAX693A
MAX800L
MAX800M
N.C. N.C.
N.C.
50kHz
Figure 3. Oscillator Circuits
Watchdog Timeout Period
OSC SEL OSC IN
Normal Immediately After Reset
Reset Timeout Period
Low External Clock Input 1024 clks 4096 clks 2048 clks
Low External Capacitor (600/47pF x C)ms (2.4/47pF x C)sec (1200/47pF x C)ms
Floating Low 100ms 1.6sec 200ms
Floating Floating 1.6sec 1.6sec 200ms
Table 1. Reset Pulse Width and Watchdog Timeout Selections