Datasheet

1.3V Comparator and Power-Fail Warning
The power-fail input (PFI) is compared to an internal
1.3V reference. The power-fail output (PFO) goes low
when the voltage at PFI is less than 1.3V. Typically, PFI is
driven by an external voltage divider which senses either
the unregulated DC input to the system’s 5V regulator or
the regulated 5V output. The voltage divider ratio can be
chosen such that the voltage at PFI falls below 1.3V sev-
eral milliseconds before the +5V supply falls below 4.75V.
PFO is normally used to interrupt the microprocessor so
that data can be stored in RAM before V
CC
falls below
4.75V and the RESET output goes low (4.5V for MAX692/
MAX693).
The power-fail detector can also monitor the backup bat-
tery to warn of a low battery condition. To conserve bat-
tery power, the power-fail detector comparator is turned
off and PFO is forced when V
CC
is lower than V
BATT
input voltage.
Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the micro-
processor. If the microprocessor does not toggle the
Watchdog Input (WDI) within the selected timeout period,
a 50ms* RESET pulse is generated. Since many systems
cannot service the watchdog timer immediately after a
reset, the MAX691/MAX693/MAX695 has a longer time-
out period after reset is issued. The normal timeout period
becomes effective following the first transition of WDI after
RESET has gone high. The watchdog timer is restarted
at the end of reset, whether the reset was caused by
lack of activity on WDI or by V
CC
falling below the reset
threshold. If WDI remains either high or low, reset pulses
will be issued every 1.6s. The watchdog monitor can be
deactivated by floating the watchdog input (WDI).
The watchdog output (WDO, MAX691/MAX693/MAX695
only) goes low if the watchdog timer times out and
remains low until set high by the next transition on the
watchdog input. WDO is also set high when V
CC
goes
below the reset threshold.
The watchdog timeout period is fixed at 1.6s and the
reset pulse width is fixed at 50ms* on the 8-pin MAX690/
MAX692/MAX694. The MAX691/MAX693/MAX695 allow
these times to be adjusted per Table 1. Figures 8 shows
various oscillator configurations.
The internal oscillator is enabled when OSC SEL is
floating. In this mode, OSC IN selects between the
1.6s and 100ms watchdog timeout periods. In either
case, immediately after a reset the timeout period 1.6s.
This gives the microprocessors time to reintialize the
system. If OSC IN is low, then the 100ms watchdog
period becomes effective after the first transition of WDI.
The software should be written such that the I/O port
driving WDI is left in its power-up reset state until the ini-
tialization routines are completed and the microprocessor
is able to toggle WDI at the minimum watchdog timeout
period of 70ms.
*200ms for MAX694
Figure 7. Watchdog Timer Block Diagram
+
-
-
+
1.0V
2.7V
V
CC
TRANSACTION
DETECTOR
WATCHDOG INPUT
HI IF WATCHDOG
INPUT IS FLOATING
FOR EACH TRANSITION
RESET
COUNTER
R Q10/12
Q6
PRESCALER
WATCHDOG
COUNTER
R
Q11
Q13
Q15
WATCHDOG
TIMEOUT
SELECTOR
LOGIC
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
WATCHDOG
FAULT FF
WATCHDOG TIMEOUT SELECT
WATCHDOG OUTPUT
10.24 kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
OSC IN PIN
LOW
LINE
RESET
FLIP FLOP
Q
S R
Q
Q
Q
LONG/SHORT
FF
S R
R
S
RESET RESET
LOW LINE
(HI IF V
CC
< 4.65V)
MAX690–MAX695 Microprocessor Supervisory Circuits
www.maximintegrated.com
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