Datasheet

MAX6892/MAX6893/MAX6894
Pin Description (continued)
PIN
MAX6892 MAX6893 MAX6894
NAME FUNCTION
25 21 — IN6
Input Voltage 6. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN6 to GND with a 0.1µF capacitor as
close to the device as possible.
26 22 — IN5
Input Voltage 5. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN5 to GND with a 0.1µF capacitor as close to the device as possible.
27 23 23 IN4
Input Voltage 4. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN4 to GND with a 0.1µF capacitor as close to the device as possible.
28 24 24 IN3
Input Voltage 3. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN3 to GND with a 0.1µF capacitor as close to the device as possible.
29 25 25 IN2
Input Voltage 2. Select undervoltage threshold using TH0–TH4. See Table 2.
Power the device through IN2–IN5 or V
CC
(see the Powering the
MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass
IN2 to GND with a 0.1µF capacitor as close to the device as possible.
30 26 26 IN1
Input Voltage 1. Select undervoltage threshold using TH0–TH4. See Table 2.
For improved noise immunity, bypass IN1 to GND with a 0.1µF capacitor as
close to the device as possible.
31 27 27 WDI
Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is
not strobed with a valid low-to-high or high-to-low transition within the watchdog
timeout period, the watchdog output asserts low. The watchdog timeout period
is externally adjustable with capacitor C
SWT
or selectable for a fixed internal
timeout period. The watchdog has a long timeout period (92.16s minimum fixed
or 64x the adjusted short timeout period) after each reset event and a short
timeout period (1.44s minimum or an adjusted timeout period) after the first
valid WDI transition.
32 28 28 PG1
Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at
IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled
high. PG1 deasserts with a factory preset timeout period of 6.25ms.
— — 5, 6, 21, 22 N.C. No Connection. Not internally connected.
——— EP
Exposed Pad. Internally connected to GND. Connect EP to GND or leave
unconnected.
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
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