Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - system monitor Serialiser TQFN 32 EP

WDI

D-PO

WDI

D-PO

WDO NOT CONNECTED TO MR

WDO CONNECTED TO MR.

OR IN2–IN5

2.5V

WDI

OR IN2–IN5

2.5V

WDI

IS THE INITIAL WATCHDOG TIMEOUT PERIOD.

RESET

WDO

RESET

Figure 2. Watchdog, Reset, and Power-Up Timing Diagram

MAX6892/MAX6893/MAX6894

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

14 ______________________________________________________________________________________

Watchdog Timer

The MAX6892/MAX6893/MAX6894s’ watchdog circuit

monitors the microprocessor’s (µP’s) activity. If the µP

does not toggle the watchdog input (WDI) within the

watchdog timeout period, the watchdog output (WDO)

asserts. The internal watchdog timer is cleared by

RESET, or by a transition at WDI (which can detect

pulses as short as 50ns). The watchdog timer remains

cleared while reset is asserted. The timer starts count-

ing as soon as WDO is released (see Figure 2).

The MAX6892/MAX6893/MAX6894 feature two modes

of watchdog timer operation: normal mode and initial

mode. At power-up, after a reset event, or after the

watchdog timer expires, the initial watchdog timeout is

active. After the first transition on WDI, the normal

watchdog timeout is active. The initial and normal

watchdog timeouts are determined by the value of the

capacitor connected between SWT and ground or by

connecting SWT to V

(see the

Selecting the Reset and

Watchdog Timeout Capacitor

section). The initial watch-

dog timeout is approximately 64 times the normal watch-

dog timeout. For example, in initial mode a 1µF capacitor

gives a watchdog timeout period of about 5min.

If WDO is connected to MR, the WDO asserts for a

short duration (~5µs), long enough to assert the RESET

output. Asserting RESET clears the watchdog timer and

WDO goes high. The reset output remains asserted for

its timeout period after a watchdog fault. The watchdog

timer stays cleared as long as RESET is low.

The watchdog timeout period is determined by the

value of the capacitor connected between SWT and

ground (see the

Selecting the Reset/Watchdog Timeout

Capacitor

section). Connect SWT to DBP to select fac-

tory-programmed watchdog timeout. To disable the

watchdog timer connect SWT to GND.