Datasheet

MAX6886
Set the RESET time delay by connecting a capacitor
from SRT to GND using the following equation:
where t
RP
is in seconds and C
SRT
is in Farads. Connect
SRT to V
CC
for a factory-default reset timeout of 200ms.
RESET is open-drain and requires an external pullup
resistor. RESET remains low for 1V ≤ V
CC
≤ 2.5V.
Applications Information
Layout and Bypassing
For better noise immunity, bypass each of the voltage-
detector inputs to GND with 0.1µF capacitors installed
as close to the device as possible. Bypass V
CC
and
DBP to GND with 1µF capacitors installed as close to
the device as possible.
C
t
x
SRT
WD
.
=
4 348 10
6
Pin-Selectable, Hex Power-Supply
Supervisory Circuit
12 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
Pin Configuration
20
+
19 18 17 16
678910
11
12
13
14
15
5
4
3
2
1
MAX6886
TQFN
TOP VIEW
SRT
RESET
SWT
GND
WDI
*EXPOSED PAD
*EXPOSED PAD CONNECTED TO GND.
IN5
IN1
IN2
IN3
IN4
IN6
DBP
V
CC
TH0
TH1
TH2
TH3
TH4
MR
MARGIN
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TQFN-EP T2055+5 21-0140 90-0010