Datasheet

MAX6884/MAX6885
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
_______________________________________________________________________________________ 5
Note 1: 100% production tested at T
A
= +25°C and T
A
= +85°C. Specifications at T
A
= -40°C are guaranteed by design.
Note 2: Device may be supplied from IN1–IN4 or V
CC
.
Note 3: The internal supply voltage, measured at V
CC
, equals the maximum of IN1–IN4.
Note 4: V
IN_
> 0.3 x ADC range.
Note 5: Does not include the inaccuracy of the 1.25V input reference voltage (MAX6884 only).
Note 6: DNL is implicitly guaranteed by design in a
Σ∆ converter.
Note 7: C
BUS
= total capacitance of one bus line in picofarads. Rise and fall times are measured between 0.1 x V
BUS
and 0.9 x
V
BUS
.
Note 8: Input filters on SDA, SCL, and A0 suppress noise spikes <50ns.
Note 9: An additional cycle is required when writing to configuration memory for the first time.
TIMING CHARACTERISTICS
(V
IN1
–V
IN4
or V
CC
= 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
IN1
= +25°C.) (Notes 1, 2, 3)
PARAMETER
SYM B O L
CONDITIONS
MIN TYP MAX
UNITS
TIMING CHARACTERISTICS (Figure 6)
Serial Clock Frequency f
SCL
400
kHz
Clock Low Period t
LOW
1.3 µs
Clock High Period t
HIGH
0.6 µs
Bus Free Time t
BUF
1.3 µs
START Setup Time t
SU:STA
0.6 µs
START Hold Time
t
HD:STA
0.6 µs
STOP Setup Time
t
SU:STO
0.6 µs
Data In Setup Time
t
SU:DAT
100
ns
Data In Hold Time
t
HD:DAT
30
900
ns
Receive SCL/SDA Minimum Rise
Time
t
R
(Note 7)
20 +
0.1 x C
BUS
ns
Receive SCL/SDA Maximum Rise
Time
t
R
(Note 7)
300
ns
Receive SCL/SDA Minimum Fall
Time
t
F
(Note 7)
20 +
0.1 x C
BUS
ns
Receive SCL/SDA Maximum Fall
Time
t
F
(Note 7)
300
ns
Transmit SDA Fall Time t
F
C
BUS
= 400pF (Note 5)
20 +
0.1 x C
BUS
300
ns
Pulse Width of Spike Suppressed
t
SP
(Note 8) 50 ns
EEPROM Byte Write Cycle Time t
WR
(Note 9) 11 ms